• Title/Summary/Keyword: efficient throughput

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Simulation-based Design and Performance Analysis of Two Phase Banker's Algorithm for Efficient Operation of Capacitated Automated Production Systems (유한용량 자동생산 시스템의 효율적인 운용을 위한 시뮬레이션 기반 2단계 은행가 알고리즘(BA) 설계 및 성능분석)

  • Shin, Hee Chul;Choi, Jin Young
    • Journal of the Korea Society for Simulation
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    • v.21 no.4
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    • pp.1-9
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    • 2012
  • This paper suggests a two-phase look-ahead Banker's algorithm for efficient operation of capacitated automated production systems. The algorithm improves the ability of detecting safe states of the previous one by considering the possibility of processing each job to completion at once as well as partial movement between jobs. The improved performance of the proposed algorithm is testified by performing numerical experiment in terms of (i) detection rate of safe states and (ii) system throughput and verified by using paired t-test.

An Efficient Hardware Implementation of Whirlpool Hash Function (Whirlpool 해쉬 함수의 효율적인 하드웨어 구현)

  • Park, Jin-Chul;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.10a
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    • pp.263-266
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    • 2012
  • This paper describes an efficient hardware implementation of Whirlpool hash function as ISO/IEC 10118-3 standard. Optimized timing is achieved by using pipelined small LUTs, and Whirlpool block cipher and key schedule have been implemented in parallel for improving throughput. In key schedule, key addition is area-optimized by using inverters and muxes instead of using rom and xor gates. This hardware has been implemented on Virtex5-XC5VSX50T FPGA device. Its maximum operating frequency is about 151MHz, and throughput is about 950Mbps.

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Hardware Design and Implementation of Block Encryption Algorithm ARIA for High Throughput (High Throughput을 위한 블록 암호 알고리즘 ARIA의 하드웨어 설계 및 구현)

  • Yoo, Heung-Ryol;Lee, Sun-Jong;Son, Yung-Deug
    • Journal of IKEEE
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    • v.22 no.1
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    • pp.104-109
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    • 2018
  • This paper presents a hardware design for the block encryption algorithm of ARIA which is used for standard in Korea. It presents a hardware-efficient design to increase the throughput for the ARIA algorithm using a high-speed pipeline architecture. We have used ROM for the S-box implementation. This approach aims to decrease the critical path delay of the encryption. In this paper, hardware was designed by VHDL, realized RTL level by Synplify which is synthesis tool and verified simulation by ModelSim. The ARIA algorithm is shown 68.3 MHz (Maximum operation frequency) to use Xilinx VertxE XCV Series device.

Statistically Controlled Opportunistic Resource Block Sharing for Femto Cell Networks

  • Shin, Dae Kyu;Choi, Wan;Yu, Takki
    • Journal of Communications and Networks
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    • v.15 no.5
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    • pp.469-475
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    • 2013
  • In this paper, we propose an efficient interference management technique which controls the number of resource blocks (or subcarriers) shared with other cells based on statistical interference levels among cells. The proposed technique tries to maximize average throughput of a femto cell user under a constraint on non-real time control of a femto cell network while guaranteeing a target throughput value of a macro cell user. In our proposed scheme, femto cells opportunistically use resource blocks allocated to other cells if the required average user throughput is not attained with the primarily allocated resource blocks. The proposed method is similar to the underlay approach in cognitive radio systems, but resource block sharing among cells is statistically controlled. For the statistical control, a femto cell sever constructs a table storing average mutual interference among cells and periodically updates the table. This statistical approach fully satisfies the constraint of non-real time control for femto cell networks. Our simulation results show that the proposed scheme achieves higher average femto user throughput than conventional frequency reuse schemes for time varying number of users.

Link Adaptation and Selection Method for OFDM Based Wireless Relay Networks

  • Can, Basak;Yomo, Hiroyuki;Carvalho, Elisabeth De
    • Journal of Communications and Networks
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    • v.9 no.2
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    • pp.118-127
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    • 2007
  • We propose a link adaptation and selection method for the links constituting an orthogonal frequency division multiplexing (OFDM) based wireless relay network. The proposed link adaptation and selection method selects the forwarding, modulation, and channel coding schemes providing the highest end-to-end throughput and decides whether to use the relay or not. The link adaptation and selection is done for each sub-channel based on instantaneous signal to interference plus noise ratio (SINR) conditions in the source-to-destination, source-to-relay and relay-to-destination links. The considered forwarding schemes are amplify and forward (AF) and simple adaptive decode and forward (DF). Efficient adaptive modulation and coding decision rules are provided for various relaying schemes. The proposed end-to-end link adaptation and selection method ensures that the end-to-end throughput is always larger than or equal to that of transmissions without relay and non-adaptive relayed transmissions. Our evaluations show that over the region where relaying improves the end-to-end throughput, the DF scheme provides significant throughput gain over the AF scheme provided that the error propagation is avoided via error detection techniques. We provide a frame structure to enable the proposed link adaptation and selection method for orthogonal frequency division multiple access (OFDMA)-time division duplex relay networks based on the IEEE 802.16e standard.

Efficient Bio-Automation System using Multi-Tasking (멀티-태스킹을 이용한 효율적인 Bio-Automation 시스템)

  • 정상용;이상호
    • Proceedings of the Korean Information Science Society Conference
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    • 2004.10b
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    • pp.271-273
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    • 2004
  • 최근의 생물학 연구는 '시스템 생물학 또는 시스템 생명공학 '으로 발전하면서 생명체 분석의 속도와 용량이 상상을 초월할 만큼 발전하고 있으며, 이것이 성공여부 판가름의 중요한 변수로 작용함에 따라 다량의 샘플들을 빠른 시간 안에 처리하기 위한 high throughput bio-automation System이 속속 개발되고 있다. 이 연구에서는 현재까지 개발되어 상용화 된 high throughput bio-automation system들의 멀티-태스킹에 있어서의 문제점을 지적하고 개선된 합리적인 멀티-태스킹을 제시하였다.스킹을 제시하였다.

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Always Metastable State True Random Number Generator

  • Seo, Hwa-Jeong;Kim, Ho-Won
    • Journal of information and communication convergence engineering
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    • v.10 no.3
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    • pp.253-257
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    • 2012
  • This paper presents an efficient filtering system for a metastable state-based true random number generator. To output a result with high randomness, we use loop-storage for storing the value of metastability. During the metastable state, the output value is accumulated to the storage. When the non-metastable state arises, the stored metastable value will be used for output instead of the result of the non-metastable state. As a result, we can maintain high entropy together with the original throughput.

Delay time Analysis of Asynchronous RIT Mode MAC in Wi-SUN (Wi-SUN에서 비동기 RIT모드 MAC의 지연시간 분석)

  • Dongwon Kim;Mi-Hee Yoon
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.24 no.2
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    • pp.65-70
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    • 2024
  • In recent years, research on smart factory wireless mobile communication technology that wirelessly remotely controls utilities is being actively conducted. The Wi-SUN (Wireless Smart Utility Network) Alliance proposed a Wi-SUN protocol structure suitable for building a platform such as a smart factory as a new wireless communication standardization standard based on EEE802.15.4g/e. It analyzes the performance of the IEEE802.15.4e Receiver Initiated Transmission(RIT) Mode Media Access Control (MAC) in terms of throughput and latency, and looks at considerations for efficient operation. RIT mode shows that as the check interval becomes longer, delay time and throughput decrease. It was shown that as the traffic load increases, if the RIT check interval is shortened, the delay time can be shortened and throughput can be increased. RIT mode has the advantage of low power consumption and has neutral characteristics between IEEE802.15.4 and CSL mode in terms of delay time and throughput.

Efficient Implementation of a Pseudorandom Sequence Generator for High-Speed Data Communications

  • Hwang, Soo-Yun;Park, Gi-Yoon;Kim, Dae-Ho;Jhang, Kyoung-Son
    • ETRI Journal
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    • v.32 no.2
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    • pp.222-229
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    • 2010
  • A conventional pseudorandom sequence generator creates only 1 bit of data per clock cycle. Therefore, it may cause a delay in data communications. In this paper, we propose an efficient implementation method for a pseudorandom sequence generator with parallel outputs. By virtue of the simple matrix multiplications, we derive a well-organized recursive formula and realize a pseudorandom sequence generator with multiple outputs. Experimental results show that, although the total area of the proposed scheme is 3% to 13% larger than that of the existing scheme, our parallel architecture improves the throughput by 2, 4, and 6 times compared with the existing scheme based on a single output. In addition, we apply our approach to a $2{\times}2$ multiple input/multiple output (MIMO) detector targeting the 3rd Generation Partnership Project Long Term Evolution (3GPP LTE) system. Therefore, the throughput of the MIMO detector is significantly enhanced by parallel processing of data communications.

A Developed Collision Resolution Algorithm in MAC Protocol for IEEE 802.11b Wireless LANs (ICEIC'04)

  • Chung Kyung Taek;Pan Ce;Park Hyun;Kim Byun Gon;Chon Byoung Sil
    • Proceedings of the IEEK Conference
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    • 2004.08c
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    • pp.681-685
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    • 2004
  • Design of efficient Medium Access Control (MAC) protocols with both high throughput performances is a major focus in distributed contention-based MAC protocol research. In this paper, we propose an efficient contention-based MAC protocol for wireless Local Area Networks, namely, the Developed Collision Resolution (DCR) algorithm. This algorithm is developed based on the following innovative ideas: to speed up the collision resolution, we actively redistribute the backoff timers for all active nodes; to reduce the average number of idle slots, we use smaller contention window sizes for nodes with successful packet transmissions and reduce the backoff timers exponentially fast when a fixed number of consecutive idle slots are detected. We show that the proposed DCR algorithm provides high throughput performance and low latency in wireless LANs.

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