• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.225-227
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• 2004

A sensor networkis composed of a large number of sensor nodes, which are densely deployed either inside the phenomenon or very close to it. One of the most important constraints on sensor nodes is the low power consumption requirement. Sensor nodes carry limited, generally irreplaceable, power sources. Therefore, while traditional networks aim to achieve high quality of service (QoS) provisions, sensor network protocols must focus primarily on power conservation. This paper presents the characteristics of energy consuming, average delay in 802.11 MAC, S-MAC that is specifically designed for wireless sensor networks. We analyze the energy consuming state in the 802.11 MAC in the simulation topology nodes, and measure average delay in 802.11 and S-MAC. Energy efficiency is the primary goal in this protocol design. 802.11 MAC is more efficient than S-MAC in the average delay, throughput. However S-MAC is an energy efficient protocol, a tradeoff between energy efficiency and delay.

• ETRI Journal
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• v.30 no.3
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• pp.451-460
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• 2008

Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as fast Fourier transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer electronics, such as wireless communications. This paper presents solutions based on parallel architectures for high throughput and power efficient FFT cores. Different combinations of hybrid low-power techniques are exploited to reduce power consumption, such as multiplierless units which replace the complex multipliers in FFTs, low-power commutators based on an advanced interconnection, and parallel-pipelined architectures. A number of FFT cores are implemented and evaluated for their power/area performance. The results show that up to 38% and 55% power savings can be achieved by the proposed pipelined FFTs and parallel-pipelined FFTs respectively, compared to the conventional pipelined FFT processor architectures.

• Journal of the Korean Operations Research and Management Science Society
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• v.30 no.2
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• pp.29-40
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• 2005

In this research, we propose packet scheduling algorithm considering different QoS characteristics of real-time traffic and non-real-time traffic in the next generation wireless communication system serving the multimedia traffic and a new efficient framing method cooperated with this packet scheduler. When the selected traffic classes of the selected users are transmitted, our proposed framing method can increase the number of serviced traffic classes by mixing the many different traffic classes within one frame considering data rate decided by the allocated AMC (Adaptive Modulation and Coding) option. Using this proposed method, the fairness among the traffic classes can be achieved and the system performance for total throughput and delay can be enhanced. Simulations are performed to analyze the performance of the proposed framing method. Our proposed packet scheduler and framing method will be applied to the next generation multimedia wireless communication system serving many traffic classes.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.605-614
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• 2016

We develop a novel SAD circuit for power-efficient H.264 encoding, namely a-SAD. Here, some highest-order MSB's are approximated to single MSB. Our theoretical estimations show that our proposed design simultaneously improves performance and power of SAD circuit, achieving good power efficiency. We decide that the optimal number of approximated MSB's is four under 8-bit YUV-420 format, the largest number not to affect video quality and compression-rate in our video experiments. In logic simulations, our a-SAD circuit shows at least 9.3% smaller critical-path delay compared to existing SAD circuits. We compare power dissipation under iso-throughput scenario, where our a-SAD circuit obtains at least 11.6% power saving compared to other designs. We perform same simulations under two- and three-stage pipelined architecture. Here, our a-SAD circuit delivers significant performance (by 13%) and power (by 17% and 15.8% for two and three stages respectively) improvements.

• ETRI Journal
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• v.28 no.6
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• pp.709-720
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• 2006

In this paper, we suggest a simple and efficient multiple-forwarder-based file distribution method which can work with a tree-based application layer multicast. Existing multiple-forwarder approaches require high control overhead. The proposed method exploits the assumption that receivers join a session at different times. In tree-based application layer multicast, a set of data packets is delivered from its parent after a receiver has joined but before the next receiver joins without overlapping that of other receivers. The proposed method selects forwarders from among the preceding receivers and the forwarder forwards data packets from the non-overlapping data packet set. Three variations of forwarder selection algorithms are proposed. The impact of the proposed algorithms is evaluated using numerical analysis. A performance evaluation using PlanetLab, a global area overlay testbed, shows that the proposed method enhances throughput while maintaining the data packet duplication ratio and control overhead significantly lower than the existing method, Bullet.

• Journal of IKEEE
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• v.11 no.4
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• pp.171-177
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• 2007

Although the Distributed Coordination Function is the fundamental access protocol of IEEE 802.11, it cannot meet the Quality of Service (QoS) requirements in general. So, the Point Coordinate Function is provided to support QoS related services. However, it has inherent problems. Access point (AP) has no knowledge of the queue status and instantaneous channel condition of stations in the system. In this paper we propose an efficient and versatile polling scheduler that shows excellent throughput and fairness performance. Comparison with well known polling schemes is provided through computer simulation under various channel situations including error prone environments.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.19-30
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• 1995

For the efficient interconnection between SMDS and LAN, an interconnection protocol architecture in the router is proposed in this paper. A control method of xongestion which is produced by this interconnection of SMDS and LAN is also proposed. Especially, the SIP level 3 of SMDS is devided into CS-SIP3 sublayer and CLNAP sublayer in order to circumvent the problems which are producted by the protocol difference of two networks and to consider the interconnection with B-ISDN in the future. In this way, the interconnection of SMDS and LAN is transparentlly achieved through CLNAP layer, and the interconnection protocol architecture becomes simple. To test the performance of the router, amodel of interconnection protocol which is proposed by this paper is simulated using sliding window flow control. The simulation results show that the throughput of router is increased. The packet delay and the rate of packet discard are also decreased.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.7
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• pp.1599-1606
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• 1997

The software RAID file system is defined as the system which distributes data redundantly across an aray of disks attached to each workstations connected on a high-speed network. This provides high throughput as well as higher availability. In this paper, we present an efficient caching scheme for the software RAID filte system. The performance of this schmem is compared to two other schemes previously proposed for convnetional file systems and adapted for the software RAID file system. As in hardware RAID systems, small-writes to be the performance bottleneck in softwre RAID filte systems. To tackle this problem, we logically divide the cache into two levels. By keeping old data and parity val7ues in the second-level cache we were able to eliminate much of the extra disk reads and writes necessary for write-back of dirty blocks. Using track driven simulations we show that the proposed scheme improves performance for both the average response time and the average system busy time.

• The Transactions of the Korea Information Processing Society
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• v.2 no.3
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• pp.382-389
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• 1995

In this paper, we propose an efficient transmission schedule which can be used in indoor wireless LAN. It reduces considerably the time delay and increases the throughput by reusing the bandwidth. We describe the architecture of the wireless LAN, the algorithm of step-by-step allocation of time slot reusing the resource and the results of the computer simulation.

• ETRI Journal
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• v.26 no.1
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• pp.21-26
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• 2004

This paper proposes a new architecture for a Viterbi decoder with an efficient memory management scheme. The trace-back operation is eliminated in the architecture and the memory storing intermediate decision information can be removed. The elimination of the trace-back operation also reduces the number of operation cycles needed to determine decision bits. The memory size of the proposed scheme is reduced to 1/($5{\times}$ constraint length) of that of the register exchange scheme, and the throughput is increased up to twice that of the trace-back scheme. A Viterbi decoder complying with the IS-95 reverse link specification is designed to verify the proposed architecture. The decoder has a code rate of 1/3, a constraint length of 9, and a trace-forward depth of 45.