• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.48-55
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• 1999

This paper describes automatic gain control circuit (AGC) design techniques for CMOS CCD camera interface systems. The required gain of the AGC in the proposed system is controlled directly by digital bits without conventional extra D/A converters and the signal settling behavior is almost independent of AGC gain variation at video speeds. A capacitor-segment combination technique to obtain large capacitance values considerably improves the effective bandwidth of the AGC based on switched-capacitor techniques. A proposed layout scheme for capacitor implementation shows AGC matching accuracy better than 0.1 %. The outputs from the AGC are transferred to a 10b A/D converter integrated on the same chip. The proposed AGC is implemented as a sub-block of a CCD camera interface system using a 0.5 um n-well CMOS process. The prototype shows the 32-dB AGC dynamic range in 1/8-dB steps with 173 mW at 3 V and 25 MHz.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.2 s.31
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• pp.29-35
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• 2004

Hafnium-oxide gate dielectric films deposited by a metal organic chemical vapor deposition technique on a $N_2-plasma$ treated SiNx and a hydrogen-terminated Si substrate have been investigated. In the case of $HfO_2$ film deposited on a hydrogen-terminated Si substrate, suppressed crystallization with effective carbon impurity reduction was obtained at $450^{\circ}C$. X-ray photoelectron spectroscopy indicated that the interface layer was Hf-silicate rather than phase separated Hf-silicide and silicon oxide structure. Capacitance-voltage measurements show equivalent oxide thickness of about 2.6nm for a 5.0 nm $HfO_2/Si$ single layer capacitor and of about 2.7 nm for a 5.7 nm $HfO_2/SiNx/Si$ stack capacitor. TEM shows that the interface of the stack capacitor is stable up to $900^{\circ}C$ for 30 sec.

• Journal of Electrochemical Science and Technology
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• v.6 no.4
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• pp.139-145
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• 2015

Capacitive deionization (CDI) process is a novel approach for desalination of an aqueous salt solution. In the present study, an activated carbon cloth (ACC) is proposed as effective electrode material. Initially the carbon cloth was activated in 1 M and 8 M HNO₃ for 9 hours at room temperature. The untreated and chemically activated carbon cloth (ACC) electrode materials were subjected to BET surface area measurements in order to get information about their specific surface area, average pore size, total pore volume and micropore area. The above materials were characterized by X-ray diffraction (XRD) and scanning electron microscope (SEM) also. The electrochemical studies for the electrodes were done using cyclic voltammetry (CV) in 0.1 M Na₂SO₄ medium. From the studies, it was found that resistivity of the activated carbon cloth electrodes (treated in 1 M and 8 M HNO₃) was decreased significantly by the chemical oxidation in nitric acid at room temperature and its capacitance was found to be 90 F/g (1 M HNO₃) and 154 F/g (8 M HNO₃) respectively in 0.1 M Na₂SO₄ solution. The capacitive deionization behavior of a single cell CDI with activated carbon cloth electrodes was also studied and reported in this work.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.71-77
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• 2009

A novel phase-locked loop(PLL) architecture with multiple charge pumps for fast locking has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. The fast locking PLL that changes its loop bandwidth through controlling charge pumps depending on locking status has been designed. The capacitor usually occupying the larger portion of the chip is also minimized with the proposed scheme. Therefore, the PLL size of $990{\mu}m\;{\times}\;670{\mu}m$ including resistors and capacitors at the bandwidth of 29.9KHz has been achieved. It has been fabricated with 3.3V $0.35{\mu}m$ CMOS process. The locking time is less than $6{\mu}s$ with the measured phase noise of -90.45dBc/Hz @1MHz at 851.2MHz output frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.14-23
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• 2011

In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.492-499
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• 2013

We have investigated the electrical properties of Ru/Ni/n-GaN Schottky structure using current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. The barrier height (${\Phi}_{bo}$) and ideality factor (n) of Ru/Ni/n-GaN Schottky structure are found to be 0.66 eV and 1.44, respectively. The ${\Phi}_{bo}$ and the series resistance ($R_S$) obtained from Cheung's method are compared with modified Norde's method, and it is seen that there is a good agreement with each other. The energy distribution of interface state density ($N_{SS}$) is determined from the I-V measurements by taking into account the bias dependence of the effective barrier height. Further, the interface state density $N_{SS}$ as determined by Terman's method is found to be $2.14{\times}10^{12}\;cm^{-2}\;eV^{-1}$ for the Ru/Ni/n-GaN diode. Results show that the interface state density and series resistance has a significant effect on the electrical characteristics of studied diode.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.9
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• pp.47-53
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• 2011

The signal transmission properties of the connector such as insertion loss and return loss are investigated using analysis procedure of S-parameter simulation, equivalent model extraction, and characteristic impedance calculation. S-parameter simulation is performed by connector's modeling and solving based on 3-dimensional finite element method. The connector's equivalent model of ${\pi}$ type is are proposed and extracted with an optimization process of circuit analysis simulator. The characteristic impedance of the connector is calculated with results of circuit analysis simulation and S-parameter data. According to the connector's characteristic impedance, it's revised design is carried out. In this work, the connector's effective contact area is increased and its body is applied as a high dielectric material in order to increase its capacitance and then obtain impedance matching. Therefore, return loss of the connector is improved by approximately 10 dB due to its design revision.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.18-27
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• 2010

In this paper, a 1.2V 7-bit 1GSPS A/D converter with offset self-calibration is proposed. The proposed A/D converter structure is based on the folding-interpolation whose folding rate is 2, interpolation rate is 8. Further, for the purpose of improving the chip performance, an offset self-calibration circuit is used. The offset self-calibration circuit reduce the variation of the offset-voltage，due to process mismatch, parasitic resistor, and parasitic capacitance. The chip has been fabricated with a 1.2V 65nm 1-poly 6-metal CMOS technology. The effective chip area is $0.87mm^2$ and the power dissipates about 110mW at 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at 800MHz sampling frequency. The measured SNDR is 3dB higher than the same circuit without any calibration.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.9 no.6
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• pp.802-812
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• 1998

Safety related to electric field exposure for the personnel of high voltage power plant and substation is of importance. To analyze the induced current influencing on human body in this paper, we calculate directly capacitance in three dimension which is complex and time consuming, as not to separate the voltage source and the induced object using a effective modeling technique. The proposed algorithm in this paper has been applied to 765 kV high voltage transmission line to evaluate human hazard for the induced current through the case study. As the results, the short circuit current of human body has been identified in the range of 0.3 mA to 6.8 mA. Closing to transmission line, this range of short current can exceed 5 mA that ANSI recommended let-go current. Therefore, it is necessary to countermeasure such as putting on conductive clothing in live-line maintenance of transmission line.

• Transactions on Electrical and Electronic Materials
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• v.16 no.1
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• pp.10-15
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• 2015

A thin-film transmission line (TFTL) employing a microstrip line/coplanar waveguide (ML/CPW) was fabricated on a silicon substrate for application to a miniaturized on-chip RF component, and the RF characteristics of the device with the proposed structure were investigated. The TFTL employing a ML/CPW composite structure exhibited a shorter wavelength than that of a conventional coplanar waveguide and that of a thin-film microstrip line. When the TFTL with the proposed structure was fabricated to have a length of ${\lambda}/8$, it showed a loss of less than 1.12 dB at up to 30 GHz. The improvement in the periodic capacitance of the TFTL caused for the propagation constant, ${\beta}$, and the effective permittivity, ${\varepsilon}_{eff}$, to have values higher than those of a device with only a conventional coplanar waveguide and a thin film microstrip line. The TFTL with the proposed structure showed a ${\beta}$ of 0.53~2.96 rad/mm and an ${\varepsilon}_{eff}$ of 22.3~25.3 when operating from 5 to 30 GHz. A highly miniaturized impedance transformer was fabricated on a silicon substrate using the proposed TFTL for application to a low-impedance transformation for broadband. The size of the impedance transformer was 0.01 mm2, which is only 1.04% of the size of a transformer fabricated using a conventional coplanar waveguide on a silicon substrate. The impedance transformer showed excellent RF performance for broadband.