• Journal of Computing Science and Engineering
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• v.4 no.3
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• pp.189-206
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• 2010

It is generally accepted that dynamic voltage scaling (DVS) is one of the most effective techniques of energy minimization for real-time applications in embedded system design. The effectiveness comes from the fact that the amount of energy consumption is quadractically proportional to the voltage applied to the processor. The penalty is the execution delay, which is linearly and inversely proportional to the voltage. According to the granularity of tasks to which voltage scaling is applied, the DVS problem is divided into two subproblems: inter-task DVS problem, in which the determination of the voltage is carried out on a task-by-task basis and the voltage assigned to the task is unchanged during the whole execution of the task, and intra-task DVS problem, in which the operating voltage of a task is dynamically adjusted according to the execution behavior to reflect the changes of the required number of cycles to finish the task before the deadline. Frequent voltage transitions may cause an adverse effect on energy minimization due to the increase of the overhead of transition time and energy. In addition, DVS needs to be carefully applied so that the dynamically varying chip temperature should not exceed a certain threshold because a drastic increase of chip temperature is highly likely to cause system function failure. This paper reviews representative works on the theoretical solutions to DVS problems regarding inter-task DVS, intra-task DVS, voltage transition, and thermal-aware DVS.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.3
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• pp.421-428
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• 2008

The DVS(Dynamic Voltage Scaling) technique is the method to reduce the dynamic energy consumption. As using slack times, it extends the execution time of the big load operations by changing the frequency and the voltage of variable voltage processors. Researches, that controlling the energy consumption of the processors and the data transmission among processors by controlling the bandwidth to reduce the energy consumption of the entire system, have been going on. Since operations in multiprocessor systems have the data dependency between processors, however, the DVS techniques devised for single processors are not suitable to improve the energy efficiency of multiprocessor systems. We propose the new scheduling algorithm based on DVS for increasing energy efficiency of multiprocessor systems. The proposed DVS algorithm can improve the energy efficiency of the entire system because it controls frequency and voltages having the data dependency among processors.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.4
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• pp.93-99
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• 2008

Portable devices generally have limited energy sources, so there is a need to minimize the power consumption of processor using energy conservation methods. One of the most common energy conservation methods is dynamic voltage scaling (DVS). In this paper, we propose a new DVS algorithm which uses workload of application to determine frequency and voltage of processors. The posed DVS algorithm consists of DVS module in kernel and specified function in application. The DVS module monitors the processor utilization and changes frequency and voltage periodically. The other part monitors workload of application. With these two procedures, the processor can change the performance level to meet their deadline while consuming less energy. We implemented the proposed DVS algorithm on PXA270 processor with Linux 2.6 kernel.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.282-285
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• 2002

In this paper, we designed of low power system by using dynamic scaling. As an effective low-power design, dynamic voltage/frequency scaling recently has received a lot of attention. In dynamic frequency scheme, all execution cycles are driven by the clock frequency that switched frequency dynamically at run time. The algorithm schedules lower frequency operators at earlier steps and higher frequency operators to later steps. This algorithm assigned the frequency for each execution cycle then it adjusted the voltage associated with the frequency.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.428-430
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• 2006

This paper proposes a new means of performance optimization for multimedia algorithm utilizing the Microscopic DVS (Dynamic Voltage Scaling). The Microscopic DVS technique controls the operating frequency and the supply voltage levels dynamically according to the processing requirement for each frame of multimedia data. The huffman decoding algorithm of MPEG-2 AAC audio decoder is optimized to maximize the power saving efficiency of Microscopic DVS technique. The experimental results show the reduction of computational complexity by more than 30% and the reduction of power consumption by more than 17% compared with those of the conventionally fast method.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.12
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• pp.544-546
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• 2006

This paper proposes a new means of performance optimization for multimedia algorithm utilizing the Microscopic DVS (Dynamic Voltage Scaling). The Microscopic DVS technique controls the operating frequency and the supply voltage levels dynamically according to the processing requirement for each frame of multimedia data. The huffman decoding algorithm of MPEG-2 AAC audio decoder is optimized to maximize the power saving efficiency of Microscopic DVS technique. The experimental results show the reduction of computational complexity by more than 30% and the reduction of power consumption by more than 17% compared with those of the conventionally fast method.

• ETRI Journal
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• v.44 no.5
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• pp.849-858
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• 2022

Dynamic voltage frequency scaling (DVFS) has been widely adopted for runtime power management of various processing units. In the case of neural processing units (NPUs), power management of neural network applications is required to adjust the frequency and voltage every layer to consider the power behavior and performance of each layer. Unfortunately, DVFS is inappropriate for layer-wise run-time power management of NPUs due to the long latency of voltage scaling compared with each layer execution time. Because the frequency scaling is fast enough to keep up with each layer, we propose a layerwise dynamic frequency scaling (DFS) technique for an NPU. Our proposed DFS exploits the highest frequency under the power limit of an NPU for each layer. To determine the highest allowable frequency, we build a power model to predict the power consumption of an NPU based on a real measurement on the fabricated NPU. Our evaluation results show that our proposed DFS improves frame per second (FPS) by 33% and saves energy by 14% on average, compared with DVFS.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.95-103
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• 2007

Dynamic voltage scaling (DVS) is a well-known and effective power management technique. While there has been research on slack distribution, voltage allocation and other aspects of DVS, its effects on non-voltage-scalable devices has hardly been considered. A DC-DC converter plays an important role in voltage generation and regulation in most embedded systems, and is an essential component in DVS-enabled systems that scale supply voltage dynamically. We introduce a power consumption model of DC-DC converters and analyze the energy consumption of the system including the DC-DC converter. We propose an energy-optimal off-line DVS scheduling algorithm for systems with DC-DC converters, and show experimentally that our algorithm outperforms existing DVS algorithms in terms of energy consumption.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2401-2409
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• 2016

Android CPU governors exploit the DVFS (Dynamic Voltage Frequency Scaling) technique. The DVFS is a power management technique where the CPU operating frequency is decreased to allow a corresponding reduction in the CPU supply voltage. The power consumed by a CPU is approximately proportional to the square of the CPU supply voltage. Therefore, lower CPU operating frequency allows the CPU supply voltage to be lowered. This helps to reduce the CPU power consumption. However, lower CPU operating frequency increases a task's execution time. Such an increase in the task's execution time makes the task's response time longer and makes the task's deadline miss occur. This finally leads to degrading the quality of service provided by the task. In this paper, we evaluated the performance of Android CPU governors in terms of the power consumption, tasks's response time and deadline miss ratio.

• ETRI Journal
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• v.33 no.3
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• pp.407-414
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• 2011

In an effort to reduce energy consumption, research into adaptive power management in real-time systems has become widespread. In this paper, a novel dynamic voltage scaling scheme is proposed for multiprocessor systems. Based on the concept of the Nash bargaining solution, a processor's clock speed and supply voltage are dynamically adjusted to satisfy these conflicting performance metrics. In addition, the proposed algorithm is implemented to react adaptively to the current system conditions by using an adaptive online approach. Simulation results clearly indicate that the superior performance of the proposed scheme can strike the appropriate performance balance between contradictory requirements.