• 전력전자학회:학술대회논문집
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• 전력전자학회 2019년도 전력전자학술대회
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• pp.50-52
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• 2019

Dynamic resistance equalization is a viable technique to balance SOC of cells in a parallel-connected battery configuration due to high equalization performance, simplicity and low-cost. However, an inappropriate design of the equalization resistor can degrade the equalization performance and increase the power loss. This paper proposes an optimization process to design the equalization resistors to minimize power loss and equalization error. The simulation results show that the optimally designed resistor significantly enhance the performance in comparison with the conventional fixed-resistor equalization.