• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.3
• /
• pp.60-68
• /
• 2008

This work describes a re-configurable 10MS/s to 100MS/s, low-power 10b two-step pipeline ADC operating at a power supply from 0.5V to 1.2V. MOS transistors with a low-threshold voltage are employed partially in the input sampling switches and differential pair of the SHA and MDAC for a proper signal swing margin at a 0.5V supply. The integrated adjustable current reference optimizes the static and dynamic performance of amplifiers at 10b accuracy with a wide range of supply voltages. A signal-isolated layout improves the capacitor mismatch of the MDAC while a switched-bias power-reduction technique reduces the power dissipation of comparators in the flash ADCs. The prototype ADC in a 0.13um CMOS process demonstrates the measured DNL and INL within 0.35LSB and 0.49LSB. The ADC with an active die area of $0.98mm^2$ shows a maximum SNDR and SFDR of 56.0dB and 69.6dB, respectively, and a power consumption of 19.2mW at a nominal condition of 0.8V and 60MS/s.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.17 no.10
• /
• pp.86-92
• /
• 2016

A high-capacity battery installed in a hybrid vehicle or electric vehicle is used to power, or as a power supply for, electric sub-assemblies. In order to use a high-capacity battery as a power supply for electric sub-assemblies, such as an electronic control unit or for lighting, radio, and navigation, there is a need for a DC converter that changes a high voltage of 240-400V to a low voltage of 12-14V, which is done with a low-voltage DC-DC converter (LDC). An LDC undergoes long-term aging so as to reduce latent defects in the production process. With regard to the usual aging method, an LDC is a DC-DC converter. So, a DC power supply is connected and used as input, and a programmable DC electronic load is the output. For stable operation, a product having a larger capacity by 10% (compared to an LDC) is used, and has a structure where electric power is dissipated into 100% heat. So, there is a problem with volume, based on the use of two pieces of equipment to test the LDC, and another problem based on the generation of heat in the programmable DC electronic load. Hence, this paper suggests a load test method as a way of recycling, where a significant portion of the electricity dissipated as heat in a load tester is returned as input. The method realizes savings of 80% or more in the electricity dissipated as heat through improvement in the efficiency of the recycling load tester.

• Journal of Radiation Protection and Research
• /
• v.18 no.1
• /
• pp.9-24
• /
• 1993

The time-dependent radioecological model applicable to Korean environment has been developed in order to assess the radiological consequences following the short-term deposition of radionuclides in an accident of nuclear power plant. Time-dependent radioactivity concentrations in foodstuffs can be estimated by the model called 'KORFOOD' as well as time-dependent and time-integrated ingestion doses. Three kinds of critical radionuclides and thirteen kinds of foodstuffs were considered in this model. Dynamic variation of radioactivities were simulated by considering several effects such as deposition, weathering and washout, resuspension, root uptake, translocation, leaching, senescence, intake and excretion of soil by animals, intake and excretion of feedstuffs by animals, etc. The input data to the KORFOOD are the time of the year when the deposition occurs, the kinds of radionuclides and foodstuffs for estimation. The time-dependent specific activities in rice and the ingestion doses due to the consumption of all considered foodstuffs were calculated with deposition time using agricultural data-base in Kori region. In order to validate results of KORFOOD, the calculated results were compared with those by a leading German model, ECOSYS-87. The comparison of results shows good agreements within a factor of ten.

• The KIPS Transactions:PartA
• /
• v.16A no.6
• /
• pp.443-452
• /
• 2009

Although 32-bit architectures are becoming the norm for modern microprocessors, 16-bit ones are still employed by many low-end processors, for which small size and low power consumption are of high priority. However, 16-bit architectures have a critical disadvantage for embedded processors that they do not provide enough encoding space to add special instructions coined for certain applications. To overcome this, many existing architectures adopt non-orthogonal, irregular instruction sets to accommodate a variety of unusual addressing modes. In general, these non-orthogonal architectures are regarded compiler-unfriendly as they tend to requires extremely sophisticated compiler techniques for optimal code generation. To address this issue, we proposed a compiler-friendly processor with a new addressing mode, called the dynamic implied addressing mode(DIAM). In this paper, we will demonstrate that the DIAM provides more encoding space for our 16-bit processor so that we are able to support more instructions specially customized for our applications. And we will explain the advanced architecture which has improved performance. In our experiment, the proposed architecture shows 11.6% performance increase on average, as compared to the basic architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.5
• /
• pp.71-81
• /
• 2008

In this paper, we propose a novel Globally Asynchronous, Locally Dynamic System(GALDS) bus and demonstrate its performance. The proposed GALDS bus is the bidirectional multitasking bus with the segmented bus architecture supporting the concurrent operation of multi-masters and multi-slaves. By analyzing system tasks, the bus architecture chooses the optimal frequency for each If among multiples of bus frequency and thus we can reduce the overall power consumption. For efficient data communications between IPs operating in different frequencies, we designed an asynchronous and bidirectional FIFO based on an asynchronous wrapper with hand-shaking interface. In addition, since systems can be easily expandable by inserting bus segments, the proposed architecture has advantages in IP reusability and structural flexibility As a test example, a four-segment bus haying four masters and four slaves were designed by using Verilog HDL. We demonstrate multitasking operations with read/write data transfers by simulation when the ratios of operation frequency are 1:1, 1:2, 1:4 and 1:8. The data transfer mode is a 16 burst increment mode compatible with Advanced Microcontroller Bus Architecture(AMBA). The maximum operation latency of the proposed GALDS bus is 22 clock cycles for the bus write operation, and 44 clock cycles for read.

• Information Systems Review
• /
• v.12 no.1
• /
• pp.189-207
• /
• 2010

We applied IT ecosystem analysis to Smart Grid system in this paper and thereby compared various arguments about Smart Grid technologies against the reality of the power generation and distribution in South Korea with a special attention to the power distribution side. Our work attempts to propose policy implications in the government-level based on a firm-level analysis using the framework of the competitive strategy and advantage. The Smart Grid initiative is expected to enhance the efficiency in the power generation and distribution. In addition, the Smart Grid initiative aims at capturing the opportunities in the electric power business such as parts, components, supplies, and system products in the global arena. Prerequisites of smart distribution system include building infrastructure based on smart distribution parts, information systems, communication technologies, and developing various application programs and interfaces that would interact with the consumers. Consumers are expected to play an integral role by changing their consumption patterns in response to dynamic pricing and quality choices enabled by the smart distribution technologies. In order to induce the consumers to participate actively in the program, firms and policy makers should consider providing consumers economic incentives and proper education for better understanding of new technologies. Our work helps policy makers and firm better understand the nature of technology and stakeholders for the successful implementation of smart distribution technologies.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.9
• /
• pp.251-258
• /
• 2012

Recently, NAND Flash memory structure is evolving from SDR (Single Data Rate) to high speed DDR(Double Data Rate) to fulfill the high performance requirement of SSD and SSS. Accordingly, the proper ways of transferring data that latches valid data stably and minimizing data skew between pins by using PHY(Physical layer) circuit techniques have became new issues. Also, rapid growth of speed in NAND flash increases the operating frequency and power consumption of NAND flash controller. Internal voltage variation margin of NAND flash controller will be narrowed through the smaller geometry and lower internal operating voltage below 1.5V. Therefore, the increase of power budge deviation limits the normal operation range of internal circuit. Affection of OCV(On Chip Variation) deteriorates the voltage variation problem and thus causes internal logic errors. In this case, it is too hard to debug, because it is not functional faults. In this paper, we propose new architecture that maintains the valid timing window in cost effective way under sudden power fluctuation cases. Simulation results show that the proposed technique minimizes the data skew by 379% with reduced area by 20% compared to using PHY circuits.

• The KIPS Transactions:PartA
• /
• v.11A no.2
• /
• pp.195-202
• /
• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.1 no.1
• /
• pp.84-93
• /
• 2001

An electromagnetic micro x-y stage for probe-based data storage (PDS) has been fabricated. The x-y stage consists of a silicon body inside which planar copper coils are embedded, a glass substrate bonded to the silicon body, and eight permanent magnets. The dimensions of flexures and copper coils were determined to yield $100{\;}\mu\textrm{m}$ in x and y directions under 50 mA of supplied current and to have 440 Hz of natural frequency. For the application to PDS devices, electromagnetic stage should have flat top surface for the prevention of its interference with multi-probe array, and have coils with low resistance for low power consumption. In order to satisfy these design criteria, conducting planar copper coils have been electroplated within silicon trenches which have high aspect ratio ($5{\;}\mu\textrm{m}$in width and $30{\;}\mu\textrm{m}$in depth). Silicon flexures with a height of $250{\;}\mu\textrm{m}$ were fabricated by using inductively coupled plasma reactive ion etching (ICP-RIE). The characteristics of a fabricated electromagnetic stage were measured by using laser doppler vibrometer (LDV) and dynamic signal analyzer (DSA). The DC gain was $0.16{\;}\mu\textrm{m}/mA$ and the maximum displacement was $42{\;}\mu\textrm{m}$ at a current of 180 mA. The measured natural frequency of the lowest mode was 325 Hz. Compared with the designed values, the lower natural frequency and DC gain of the fabricated device are due to the reverse-tapered ICP-RIE process and the incomplete assembly of the upper-sided permanent magnets for LDV measurements.

• Investigative Magnetic Resonance Imaging
• /
• v.22 no.1
• /
• pp.26-36
• /
• 2018

Purpose: Children born with single ventricle physiology demonstrate poor growth rate and suffer from malnutrition, which lead to increased morbidity and mortality in this population. We assume that an anabolic steroid, oxandrolone, will promote growth in these infants by improving myocardial energy utilization. The purpose of this paper is to study the efficacy of oxandrolone on myocardial energy consumption in these infants. Materials and Methods: We modeled single ventricle physiology in a lamb by prenatally shunting the aorta to the pulmonary artery and then postnatally, we monitored cardiac energy utilization by quantitatively measuring the first order reaction rate constant, $k_f$ of the creatine-kinase reaction in the heart using magnetization transfer $^{31}P$ magnetic resonance spectroscopy, home built $^1H/^{31}P$ transmit/receive double tuned coil, and transmit/receive switch. We also performed cine MRI to study the structure and dynamic function of the myocardium and the left ventricular chamber. The spectroscopy data were processed using home-developed python software, while cine data were analyzed using Argus software. Results: We quantitatively measured both the first order reaction rate constant and ejection fraction in the control, shunted, and the oxandrolone-treated lambs. Both $k_f$ and ejection fraction were found to be more significantly reduced in the shunted lambs compared to the control lambs, and they are increased in oxandrolone-treated lambs. Conclusion: Some improvement was observed in both the first order reaction rate constant and ejection fraction for the lamb treated with oxandrolone in our preliminary study.