• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.6
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• pp.1892-1912
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• 2022

With the massive demand and growth of cloud computing, virtualization plays an important role in providing services to end-users efficiently. However, with the increase in services over Cloud Computing, it is becoming more challenging to manage and run multiple Virtual Machines (VMs) in Cloud Computing because of excessive power consumption. It is thus important to overcome these challenges by adopting an efficient technique to manage and monitor the status of VMs in a cloud environment. Reduction of power/energy consumption can be done by managing VMs more effectively in the datacenters of the cloud environment by switching between the active and inactive states of a VM. As a result, energy consumption reduces carbon emissions, leading to green cloud computing. The proposed Efficient Dynamic VM Scheduling approach minimizes Service Level Agreement (SLA) violations and manages VM migration by lowering the energy consumption effectively along with the balanced load. In the proposed work, VM Scheduling for Efficient Dynamically Migrated VM (VMS-EDMVM) approach first detects the over-utilized host using the Modified Weighted Linear Regression (MWLR) algorithm and along with the dynamic utilization model for an underutilized host. Maximum Power Reduction and Reduced Time (MPRRT) approach has been developed for the VM selection followed by a two-phase Best-Fit CPU, BW (BFCB) VM Scheduling mechanism which is simulated in CloudSim based on the adaptive utilization threshold base. The proposed work achieved a Power consumption of 108.45 kWh, and the total SLA violation was 0.1%. The VM migration count was reduced to 2,202 times, revealing better performance as compared to other methods mentioned in this paper.

• ETRI Journal
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• v.37 no.1
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• pp.157-164
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• 2015

As GPU power consumption in smartphones increases with more advanced graphic performance, it becomes essential to estimate GPU power consumption accurately. The conventional GPU power model assumes, simply, that a GPU consumes constant power when turned on; however, this is no longer true for recent smartphone GPUs. In this paper, we propose an accurate GPU power model for smartphones, considering newly adopted dynamic voltage and frequency scaling. For the proposed GPU power model, our evaluation results show that the error rate for system power estimation is as low as 2.9%, on average, and 4.6% in the worst case.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.52-60
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• 2010

In this paper, we propose a dynamic power management framework for multi-core systems. We reduced the power consumption of multi-core processors such as Intel Centrino Duo and ARM11 MPCore, which have been used at the consumer electronics and personal computer market. Each processor uses a different technique to save its power usage, but there is no embedded multi-core processor which has a precise power control mechanism such as dynamic voltage scaling technique. The proposed dynamic power management framework is suitable for smart phones which have an operating system to provide multi-processing capability. Basically, our framework follows an intuitive idea that reducing the power consumption of idle cores is the most effective way to save the overall power consumption of a multi-core processor. We could minimize the energy consumption used by idle cores with application-targeted policies that reflect the characteristics of active workloads. We defined some properties of an application to analyze the performance requirement in real time and automated the management process to verify the result quickly. We tested the proposed framework with popular processors such as Intel Centrino Duo and ARM11 MPCore, and were able to find that our framework dynamically reduced the power consumption of multi-core processors and satisfied the performance requirement of each program.

• Journal of information and communication convergence engineering
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• v.9 no.6
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• pp.625-628
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• 2011

Dynamic sensor network(DSN) technology which is based on swarming flight type air node offers analyzed and acquired information on target data gathered by air nodes in rotation flight or 3 dimension array flight. Efficient operation of dynamic sensor network based on air node is possible when problems of processing time, data transmission reliability, power consumption and intermittent connectivity are solved. Delay tolerant network (DTN) can be a desirable alternative to solve those problems. DTN using store-and-forward message switching technology is a solution to intermittent network connectivity, long and variable delay time, asymmetric data rates, and high error rates. However, all processes are performed at the bundle layer, so high power consumption, long processing time, and repeated reliability technique occur. DSN based on swarming flight type air node need to adopt store-and-forward message switching technique of DTN, the cancelation scheme of repeated reliability technique, fast processing time with simplified layer composition.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.241-251
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• 2007

Energy consumption in the instruction cacheaccounts for a significant portion of the total processor energy consumption. Therefore, reducing energy consumption in the instruction cache is important in designing embedded processors. This paper proposes a method for reducing dynamic energy consumption in the instruction cache by partitioning it to smaller (less energy-consuming) sub-caches. When a request comes into the proposed cache, only one sub-cache is accessed by utilizing the locality of applications. By contrast, the other sub-caches are not accessed, leading todynamic energy reduction. In addition, the proposed cache reduces dynamic energy consumption by eliminating the energy consumed in tag matching. We evaluated the energy efficiency by running cycle accurate simulator, SimpleScalar. with power parameters obtained from CACTI. Simulation results show that the proposed cache reduces dynamic energy consumption by $37%{\sim}60%$ compared to the traditional direct-mapped instruction cache.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.11
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• pp.801-805
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• 2009

Hardware based dynamic voltage and frequency scaling is a promising technique to reduce power consumption in a globally asynchronous locally synchronous system such as a homogeneous or heterogeneous multi-core system. In this paper, FPGA prototype design of hardware based dynamic frequency scaling is proposed. The proposed techniques are applied to a FIFO based multi-core system for a software defined radio and Network-on-Chip based hardware MPEG2 encoder. Compared with a references system using a single global clock, the first prototype design reduces the power consumption by 78%, but decreases the performance by 5.9%. The second prototype design shows that power consumption decreases by 29.1% while performance decreases by 0.36%.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.30 no.3
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• pp.1-8
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• 2016

In this paper, we proposed a new driving scheme to reduce the motion blur and save the power for OLEDs(organic light emitting diodes). We adopted a DVS (dynamic voltage scaling) method to reduce power consumption and the division of TV field to improve motion blur. In the proposed scheme, BEW (Blur Edge Width) was decreased to the ratio of 1/4 compared to the conventional scheme under the optimal conditions. In this scheme, the gray levels to which the DVS method can be applied were divided into much smaller groups depending on the number of subfields. Therefore, our scheme does not guarantee less power consumption for every image compared to the conventional scheme. However, the new scheme can move the gray levels adopting the DVS to higher gray levels. Thus, we can save power even when having images at high gray levels.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.3
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• pp.65-75
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• 1998

We consider connection-oriented wireless cellular networks such as the second generation wireless cellular networks and wirelss ATM networks. In these networks, a separate forward signaling channel is provided for the transmission of paging and channel allocation packets. When a call destined to a user is requested, all the base stations in the user's current location area broadcast the corresponding paging packet across forward signaling channels. By slot mode operation and paging group allocation for fusers in a location area, we can reduce relative power consumption level at battery-operated terminals. However, a sthe number of paging groups is increased for lowering relative power consumption level, a paging packet experiences higher delay to access the forward signaling channel. For the pre-negotiated quality-of-service level, paging packet delay level must be limited. In this paper, we consider static and dynamic multiplexing schemes for paging packets, and develop an analytical method for calculating paging packet delay and relative power consumption levels. Using this analytial method, we investigate the effect of network parameters on the paging packet delay and relative power consumption levels.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.446-449
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• 2004

We developed a dynamic logic architecture which resulted better leakage current, lower power consumption and less area compared to the conventional dynamic logic structures. We demonstrated the advantage from HSPICE simulation and test chip design has been completed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.9-17
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• 2011

As semiconductor process rapidly developed, the density of chips becomes higher and the space between adjacent lines narrows smaller. This trend increases the capacitance and inductance in interconnects and the coupling-capacitance of adjacent lines grows even bigger than the self-capacitance of themselves, especially in global interconnects. Inductive and capacitive coupling observed in these phenomena may cause serious problems in signal integrity. This paper proposes a codeword generation technique using extra interconnect lines to reduce the crosstalk caused by inductive and capacitive coupling and to reduce dynamic power consumption considering probability of input data. To estimate the performance of the proposed technique, the experimental results have been obtained using FastCap, FastHenry and HSPICE, and it has been shown that the power consumption using the proposed technique has yielded approximately 15% less than the results of the previous technique.