• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.355-358
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• 2010

As CMOS technology continues to scale down, signal processing is favorably done in the digital domain, which requires Analog-to-Digital (A/D) Converter to be integrated on-chip. This paper presents a design methodology of 12-bit 1-MS/s Rail-to-Rail fully differential SAR ADC using Deep N-well Switch based on binary search algorithm. Proposed A/D Converter has the following architecture and techniques. Firstly, chip size and power consumption is reduced due to split capacitor array architecture and charge recycling method. Secondly, fully differential architecture is used to reduce noise between the digital part and converters. Finally, to reduce the mismatch effect and noise error, the circuit is designed to be available for Rail-to-Rail input range using simple Deep N-well switch. The A/D Converter fabricated in a TSMC 0.18um 1P6M CMOS technology and has a Signal-to-Noise-and-Distortion-Ratio(SNDR) of 69 dB and Free-Dynamic-Range (SFDR) of 73 dB. The occupied active area is $0.6mm^2$.

• Proceedings of the SAREK Conference
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• 2008.11a
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• pp.387-392
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• 2008

In order to improve the efficiency of the main transformer in a tilting train, the optimal operation of a cooling system is necessary. For the development of the optimal control algorithm of a cooling system, the mathematical model of a main transformer cooling system was developed. This includes the dynamic model of a main transformer, an oil pump, an oil cooler and a blower. The system algorithm of a cooling system, which consists of the temperature setpoint algorithm and the temperature control algorithm, was developed. Optimal oil temperatures of the inlet and the outlet of the main transformer were obtained by considering the total electric power consumption of the system. The oil inlet temperature was controlled by the blower and the oil outlet temperature was controlled by the oil pump. A simulation program was developed by using the mathematical model and the system algorithm. Simulation results showed that the system algorithm developed from this study may be effectively used to control the main transformer cooling system in a tilting train.

• ETRI Journal
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• v.33 no.6
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• pp.897-903
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• 2011

A hybrid ${\Delta}{\Sigma}$ modulator for audio applications is presented in this paper. The pulse generator for digital-to-analog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and temperature changes. The input resistor network in the first integrator offers a gain control function in a dB-linear fashion. Also, careful chopper stabilization implementation using return-to-zero scheme in the first continuous-time integrator minimizes both the influence of flicker noise and inflow noise due to chopping. The chip is implemented in a 0.13 ${\mu}m$ CMOS technology (I/O devices) and occupies an active area of 0.37 $mm^2$. The ${\Delta}{\Sigma}$ modulator achieves a dynamic range (A-weighted) of 97.8 dB and a peak signal-to-noise-plus-distortion ratio of 90.0 dB over an audio bandwidth of 20 kHz with a 4.4 mW power consumption from 3.3 V. Also, the gain of the modulator is controlled from -9.5 dB to 8.5 dB, and the performance of the modulator is maintained up to 5 nsRMS external clock jitter.

• International Journal of Computer Science & Network Security
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• v.21 no.2
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• pp.158-170
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• 2021

Virtualization technologies are being adopted and broadly utilized in many fields and at different levels. In cloud computing, achieving load balancing across large distributed virtual machines is considered a complex optimization problem with an essential importance in cloud computing systems and data centers as the overloading or underloading of tasks on VMs may cause multiple issues in the cloud system like longer execution time, machine failure, high power consumption, etc. Therefore, load balancing mechanism is an important aspect in cloud computing that assist in overcoming different performance issues. In this research, we propose a new approach that combines the advantages of different task allocation algorithms like Round robin algorithm, and Random allocation with different threshold techniques like the VM utilization and the number of allocation counts using least connection mechanism. We performed extensive simulations and experiments that augment different scheduling policies to overcome the resource utilization problem without compromising other performance measures like makespan and execution time of the tasks. The proposed system provided better results compared to the original round robin as it takes into consideration the dynamic state of the system.

• Journal of information and communication convergence engineering
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• v.20 no.2
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• pp.137-142
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• 2022

Monolithic three-dimensional (M3D) logics such as M3D-NAND, M3D-NOR, M3D-buffer, M3D 2×1 multiplexer, and M3D D flip-flop, consisting of modularized M3D inverters (M3D-INVs), have been proposed. In the previous M3D logic, each M3D logic had to be designed separately for a standard cell library. The proposed M3D logic is designed by placing modularized M3D-INVs and connecting interconnects such as metal lines or monolithic inter-tier-vias between M3D-INVs. The electrical characteristics of the previous and proposed M3D logics were simulated using the technology computer-aided design and Simulation Program with Integrated Circuit Emphasis with the extracted parameters of the previously developed LETI-UTSOI MOSFET model for n- and p-type MOSFETs and the extracted external capacitances. The area, propagation delay, falling/rising times, and dynamic power consumption of the proposed M3D logic are lower than those of previous versions. Despite the larger space and lower performance of the proposed M3D logic in comparison to the previous versions, it can be easily designed with a single modularized M3D-INV and without having to design all layouts of the logic gates separately.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.05a
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• pp.646-648
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• 2021

Sensors with wireless communication functions are essential for acquiring and transmitting spatio-temporal data that is not easily accessible in sensor network environments. However, these sensors lack adaptability to large amounts of sensing data processing or dynamic environments, resulting in over-consumption of power and network overhead. This paper proposes a mobile agent that can acquire, transmit, and process only the necessary data by applying thresholds, and presents methods for autonomous migration and communication processing of mobile agents.

• KIISE Transactions on Computing Practices
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• v.24 no.1
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• pp.10-16
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• 2018

The task of consolidating server workloads is critical for the efficiency of a datacenter in terms of reducing costs. However, as a greater number of workloads are consolidated in a single server, the performance of workloads might be degraded due to their contention to the limited shared resources. To reduce the performance degradation, scheduling for mitigating the contention of shared resources is necessary. In this paper, we present the Dynamic Voltage Frequency Scaling (DVFS) based memory-contention aware scheduling method for multi-threaded workloads. The proposed method uses two approaches: running memory-intensive threads on the limited cores to avoid concurrent memory accesses, and reducing the frequencies of the cores that run memory-intensive threads. With the proposed algorithm, we increased performance by 43% and reduced power consumption by 38% compared to the Completely Fair Scheduler(CFS), the default scheduler of Linux.

• Journal of the Korean Society for Geothermal and Hydrothermal Energy
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• v.7 no.1
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• pp.45-50
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• 2011

Hybrid desiccant cooling system(HDCS) consists of desiccant rotor, regenerative evaporative cooler, heat pump and district heating hot water coil. In this study, TRNSYS and EES, dynamic and steady simulation programs were used for studying hybrid desiccant cooling system which is applied to an apartment house from June to August. The results show that power consumption of the hybrid desiccant cooling system is 70 kWh in June, 199 kWh in July and 241 kWh in August. Sensible and latent heats removed by the hybrid desiccant cooling system are 300 kWh, 301 kWh in June, 610 kWh, 858 kWh in July and 719 kWh, 1010 kWh in August. COP of the hybrid desiccant cooling system is 8.6 in June, 7.4 in July and 7.2 in August. COP of the hybrid desiccant cooling system decreases when latent heat load increases. Operation time of the system is 70 hours in June, 190 hours in July and 229 hours in August. Since the cooling load is largest in August, the operation time of August is longest for maintaining the indoor temperature at $26^{\circ}C$. Due to the characteristics of hybrid desiccant cooling system for efficiently handling both sensible and latent loads, this system can handle sensible and latent heat loads efficiently in summer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.6
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• pp.1321-1326
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• 2015

The amount of smart phones has increased exponentially. Due to the periodic release of high-performance smart phones and upgraded operating system, new smart phones become out-dated over 1 or 2 years. In order to solve environmental constraints of these smart phones, virtualization technology using Thin-Client terminal has been developed. However, in the case of Virtual Machine(VM), the applications associated with sensors and a GPS device can not run because they are not included. In this paper, by implementing the device driver for Android running in a virtual machine in the x86-based systems, it is to provide Android virtualization capabilities such as using the latest smart phones in the virtual machine environment. It would like to propose a method that the virtual device driver receives sensors and GPS information from the old Android smart phones(Thin-Client) that actually work and run as if the real device exists.

• Journal of Sensor Science and Technology
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• v.23 no.5
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• pp.332-336
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• 2014

In this paper, we propose a complementary metal oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) PMOSFET-type photodetector for high-speed operation. The GBT photodetector of an active pixel sensor (APS) consists of a floating gate ($n^+$-polysilicon) tied to the body (n-well) of the PMOSFET. The p-n junction photodiode that is used in a conventional APS has a good dynamic range but low photosensitivity. On the other hand, a high-gain GBT photodetector has a high level of photosensitivity but a narrow dynamic range. In addition, the pixel size of the GBT photodetector APS is less than that of the conventional photodiode APS because of its use of a PMOSFET-type photodetector, enabling increased image resolution. A CMOS binary image sensor can be designed with simple circuits, as a complex analog to digital converter (ADC) is not required for binary processing. Because of this feature, the binary image sensor has low power consumption and high speed, with the ability to switch back and forth between a binary mode and an analog mode. The proposed CMOS binary image sensor was simulated and designed using a standard CMOS $0.18{\mu}m$ process.