• Title/Summary/Keyword: dynamic power consumption

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Design of Torsion-typed Smooth Picture Actuator for DLP Projection TV

  • Moon, Yang-Ho
    • 한국정보디스플레이학회:학술대회논문집
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    • 2006.08a
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    • pp.564-568
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    • 2006
  • Smooth picture module is operated by vibration to tilt the light from the DMD (digital micro mirror device) of DLP projection TV, which makes the screen of the TV smoother and DMD chip cost lower. To satisfy the vibration characteristics of smooth picture module, it is designed by optimizing moment of inertia, spring constant and damping coefficient, using structural and fluid dynamic simulation that showed a good agreement with experimental data. To reduce the material cost and moment of inertia, engineering plastic is used and the reliability is estimated. A VCM (voice coil motor) type actuator for smooth picture has to satisfy performance requirements such as higher driving force, lower power consumption, and lower cost. The initial design and optimization for VCM was performed using FE analysis. It allowed us to optimize the design of magnetic circuit of the proposed actuator to obtain higher force while maintaining a lower cost.

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Using Bluetooth Module for Real-time Image Surveillance System (Bluetooth Module을 이용한 실시간 영상감시 시스템)

  • Seo, Yoon-Seok;Kwak, Jae-Hyuk;Lim, Joon-Hong
    • Proceedings of the KIEE Conference
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    • 2005.10b
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    • pp.337-339
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    • 2005
  • The demand for a real-time image surveillance system using network camera server is increasing as the network infra has been grown and digital video compression techniques have been developed. The image surveillance system using network camera server has several merits compared to existing real-time image surveillance system using CCTV. It would be more convenient if wireless realtime image transmission were possible. In this paper, a bluetooth module is designed and implemented for a real-time image surveillance system to send and receive informations wirelessly. It may simplify the system development procedures and increase the productivity by low power consumption, low cost, and simple wireless installation. A scatter-net formation is proposed using dynamic and distributed algorithm so that the network connection is reliable.

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Performance of capacitorless 1T-DRAM cell on silicon-germanium-on-insulator (SGOI) substrate (SGOI 기판을 이용한 1T-DRAM에 관한 연구)

  • Jung, Seung-Min;Oh, Jun-Seok;Kim, Min-Soo;Cho, Won-Ju
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.346-346
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    • 2010
  • A capacitorless one transistor dynamic random access memory (1T-DRAM) on silicon-germanium-on-insulator substrate was investigated. SGOI technology can make high effective mobility because of lattice mismatch between the Si channel and the SiGe buffer layer. To evaluate memory characteristics of 1T-DRAM, the floating body effect is generated by impact ionization (II) and gate induced drain leakage (GIDL) current. Compared with use of impact ionization current, the use of GIDL current leads to low power consumption and larger sense margin.

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WARP: Memory Subsystem Effective for Wrapping Bursts of a Cache

  • Jang, Wooyoung
    • ETRI Journal
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    • v.39 no.3
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    • pp.428-436
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    • 2017
  • State-of-the-art processors require increasingly complicated memory services for high performance and low power consumption. In particular, they request transfers within a burst in a wrap-around order to minimize the miss penalty of a cache. However, synchronous dynamic random access memories (SDRAMs) do not always generate transfers in the wrap-round order required by the processors. Thus, a memory subsystem rearranges the SDRAM transfers in the wrap-around order, but the rearrangement process may increase memory latency and waste the bandwidth of on-chip interconnects. In this paper, we present a memory subsystem that is effective for the wrapping bursts of a cache. The proposed memory subsystem makes SDRAMs generate transfers in an intermediate order, where the transfers are rearranged in the wrap-around order with minimal penalties. Then, the transfers are delivered with priority, depending on the program locality in space. Experimental results showed that the proposed memory subsystem minimizes the memory performance loss resulting from wrapping bursts and, thus, improves program execution time.

A Fundamental Study of the Bonded SOI Water Manufacturing (Bonded SOI 웨이퍼 제조를 위한 기초연구)

  • 문도민;강성건;정해도
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1997.04a
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    • pp.921-926
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    • 1997
  • SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.

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An Entropy-based Stability Algorithm for Regulating the Movement of MANET Nodes

  • Kim, Sang-Chul
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.5 no.5
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    • pp.999-1012
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    • 2011
  • This paper proposes an algorithm that enables mobile nodes to implement self-regulated movements in mobile ad-hoc networks (MANETs). It is important for mobile nodes to maintain a certain level of network-based stability by harmonizing these nodes' movements autonomously due to their limited transmission range and dynamic topology. Entropy methods based on relative position are suggested, as a means for mobile nodes to regulate their local movements. Simulations show that an early warning mechanism is suitable to maintain movement-based stability. Isolation can be reduced by 99%, with an increased network cost of 12% higher power consumption, using the proposed algorithm.

Bio-MAC: Optimal MAC Protocol for Various Bio-signal Transmission in the WBSN Environment (Bio-MAC: WBSN환경에서 다양한 생체신호 전송을 위한 최적화된 MAC Protocol)

  • Jang, Bong-Mun;Ro, Young-Sin;Yoo, Sun-Kook
    • Proceedings of the KIEE Conference
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    • 2007.04a
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    • pp.423-425
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    • 2007
  • In this paper, Medium Access Control(MAC) protocol designed for Wireless Body area Sensor Network(Bio-MAC) is proposed, Because in WBSN, the number of node is limited and each node has different characteristics. Also, reliability in transmitting vital data sensed at each node and periodic transmission should be considered so that general MAC protocol cannot satisfy such requirements of biomedical sensors in WBSN. Bio-MAC aims at optimal MAC protocol in WBSN. For this, Bio-MAC used Pattern -SuperFrame, which modified IEE E 802.15.4-based SuperFrame structurely. Bio-MAC based on TDMA uses Medium Access-priority and Pattern eXchange -Beacon method for dynamic slot allocation by considering critical sensing data or power consumption level of sensor no de etc. Also, because of the least delay time. Bio-MAC is suitable in the periodic transmission of vital signal data. The simulation results demonstrate that a efficient performance in WBSN can be achieved through the proposed Bio-MAC.

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Energy Aware Scheduling of Aperiodic Real-Time Tasks on Multiprocessor Systems

  • Anne, Naveen;Muthukumar, Venkatesan
    • Journal of Computing Science and Engineering
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    • v.7 no.1
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    • pp.30-43
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    • 2013
  • Multicore and multiprocessor systems with dynamic voltage scaling architectures are being used as one of the solutions to satisfy the growing needs of high performance applications with low power constraints. An important aspect that has propelled this solution is effective task/application scheduling and mapping algorithms for multiprocessor systems. This work proposes an energy aware, offline, probability-based unified scheduling and mapping algorithm for multiprocessor systems, to minimize the number of processors used, maximize the utilization of the processors, and optimize the energy consumption of the multiprocessor system. The proposed algorithm is implemented, simulated and evaluated with synthetic task graphs, and compared with classical scheduling algorithms for the number of processors required, utilization of processors, and energy consumed by the processors for execution of the application task graphs.

Optimal design of the suspension stiffness in HDD for improving the load/unload performance (램프 로드-언로드 특성 향상을 위한 서스펜션강성 최적설계)

  • 강태식;김태수;이철우
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2003.11a
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    • pp.898-901
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    • 2003
  • In order to get the drive reliability and low Power-consumption characteristics, most of small form factor HDD has und the load/unload mechanism instead of CSS type. Compared with CSS mechanism, the load/unload system has little opportunity of head/media contact during the disk spin-up and down. However, the load/unload mechanism needs the precise integration technology with slider, suspension, ramp and load/unload velocity, and all of these component s should be designed simultaneously, not an individually. In this paper, we focus the design of the suspension stiffness using the specified ABS design. We use the CML software to calculate the load/unload dynamic and use the RSM(Response surface method) to get the optimal condition of the suspension stiffness.

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Implementation of 2-D DCT/IDCT VLSI based on Fully Bit-Serial Architecture (완전 비트 순차 구조에 근거한 2차원 DCT/IDCT VLSI 구현)

  • 임호근;류근장;권용무;김형곤
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.6
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    • pp.188-198
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    • 1994
  • The distributed arithmetic approach has been commonly recognized as an efficient method to implement the inner-product type of computation with fixed coefficients such as DCT/IDCT. This paper presents a novel architecture and the implementation of 2-D DCT/IDCT VLSI chip based on distributed arithmetic. The main feature of the proposed architecture is a fully 2-bit serial pipeline and parallel structure with memory-based signal processing circuitry, which is efficient to the implementation of the bit-serial operation of distributed arithmetic. All modules of the proposed architecture are designed with NP-dynamic circuitry to reduce the power consumption and to increase the performance. This chip is applicable in HDTV systems working at video sampling rate up to 75 MHz.

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