• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.5
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• pp.376-383
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• 2022

The improved performance of computer parts, such as graphic card, CPU, and main board, has led to the need for power supplies with a high power output. The dynamic load profile rapidly changes the usage of power consumption depending on load operations, such as PC power and air conditioner. Under dynamic load profile conditions, power consumption can be classified into maximum, normal, and standby power. Several problems arise in the case of maximum power. Peak power is generated at the system power source in the maximum-power situation. Frequent generation of peak power can cause high-frequency problems and reduce the life of high-pressure parts (especially high-pressure capacitors). For example, when a plurality of PCs are used, system overload occurs due to peak power generation and causes problems, such as power failure and increase in electricity bills due to exceeded contract power. To solve this problem, a system peak power limit/compensation power circuit is proposed for a power supply under dynamic load profile conditions. The proposed circuit detects the system current to determine the power situation of the load. When the system current is higher than the set level, the circuit recognizes that the system current generates peak power and compensates for the load power through a converter using a super capacitor as the power source. Thus, the peak power of loads with a dynamic load profile is limited and compensated for, and problems, such as high-frequency issues, are solved. In addition, the life of high-pressure parts is increased.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.6B
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• pp.641-647
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• 2009

This paper proposes an improved predictive dynamic power management (DPM) scheme and a task scheduling algorithm to reduce unnecessary power consumption in embedded systems. The proposed algorithm performs pre-scheduling to minimize unnecessary power consumption. The proposed predictive DPM utilizes a scheduling library provided by the system to reduce computation overhead. Experimental results show that the proposed algorithm can reduce power consumption by 22.3% on the average comparing with the LLF algorithm for DPM-enable system scheduling.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.402-403
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• 2009

A variety of power reduction technologies is introduced and the benefits of the technologies are discussed. PenTile$^{(R)}$ DBLC (Dynamic Brightness LED Control) combined with SABC (Sensor-Based Adaptive Brightness Control) enables to achieve the average LED power consumption to one third. The panel power reduction of 25% can be achieved with low power driving technology, ALS (Active Level Shifter). MIP (Memory In Pixel) is expected to be useful in transflective display because the whole display area can be utilized in reflective mode with power consumption of 1mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.37-43
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• 2008

This paper introduces a high-speed low-power self-timed current-mode logic (STCML) that reduces both dynamic and leakage power dissipation. STCML significantly reduces the leakage portion of the power consumption using a pulse-mode control for shorting the virtual ground node. The proposed logic style also minimizes the dynamic portion of the power consumption due to short-circuit current by employing an enhanced self-timing buffer. Comparison results using a 80-nm CMOS technology show that STCML achieves 26 times reduction on leakage power consumption and 27% reduction on dynamic power consumption as compared to the conventional current-mode logic. They also indicate that up to 59% reduction on leakage power consumption compared to differential cascode voltage switch logic (DCVS).

• The Journal of the Korea institute of electronic communication sciences
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• v.2 no.3
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• pp.163-167
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• 2007

In this paper, to design 8 bit RISC Microprocessor, a method of Clock Gating to reduce electric power consumption is proposed. In order to examine the priority, the comparison results of between a 8 bit Microprocessor which is not considered Low Power consumption and which is considered Low Power consumption using a methods of Clock Gating are represented. Within the a few periods, the results of comparing with a Microprocessor not considered the utilization of Clock Gating shows that the reduction of dynamic dissipation is minimized up to 21.56%.

• International Journal of Contents
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• v.7 no.1
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• pp.1-7
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• 2011

A new power control algorithm for wireless communication which can be applied to various near distance communications and USN/RFID systems is proposed. This technique has been applied and tested to lithium coin battery operated UHF/microwave transceiver systems to show extremely long communication life time without battery exchange. The power control algorithm is based on the dynamic prediction method of arrival time for incoming packet at the receiver. We obtain 16mA current consumption in the TX module and 20mA current consumption in the RX module. The advantage provided by this method compared to others is that both master transceiver and slave transceiver can be low power consumption system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2401-2409
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• 2016

Android CPU governors exploit the DVFS (Dynamic Voltage Frequency Scaling) technique. The DVFS is a power management technique where the CPU operating frequency is decreased to allow a corresponding reduction in the CPU supply voltage. The power consumed by a CPU is approximately proportional to the square of the CPU supply voltage. Therefore, lower CPU operating frequency allows the CPU supply voltage to be lowered. This helps to reduce the CPU power consumption. However, lower CPU operating frequency increases a task's execution time. Such an increase in the task's execution time makes the task's response time longer and makes the task's deadline miss occur. This finally leads to degrading the quality of service provided by the task. In this paper, we evaluated the performance of Android CPU governors in terms of the power consumption, tasks's response time and deadline miss ratio.

• IEIE Transactions on Smart Processing and Computing
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• v.2 no.4
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• pp.248-254
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• 2013

The size and power consumption of digital circuits including the dimming circuit part will increase for high-performance solid state lighting (SSL) systems in the future. This study examined the low-power consumption of adiabatic dynamic CMOS logic (ADCL) due to the principles of adiabatic charging. Furthermore, the designed low-power ADCL digital pulse width modulation (PWM) was optimized for SSL dimming systems. For this purpose, an ADCL digital 3-bit PWM was optimized in two steps. In the first step, the architecture of the ADCL digital 3-bit PWM was miniaturized. In the second step, the clock cut-off circuit was designed and added to the ADCL PWM. As a result, compared to the original configuration, 60 transistors and 15 capacitors of ADCL digital 3-bit PWM were reduced for miniaturization. Moreover, the clock cut-off circuit, which controls wake-up and sleep mode of ADCL D-FFs, was designed. The power consumption of an optimized ADCL digital PWM for all bit patterns decreased by 54 %.

• Journal of Korea Society of Digital Industry and Information Management
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• v.4 no.1
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• pp.9-16
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• 2008

This paper presents a frequency selection algorithm for minimization power consumption of processor in Mobile System. The proposed algorithm has processor designed low power processor using clock gating method. Clock gating method has improved the power dissipation by control main clock through the bus which is embedded clock block applying the method of clock gating. Proposed method has compared power consumption considered the dynamic power for processor, selected frequency has considered energy gain and energy consumption for designed processor. Or reduced power consumption with decreased processor speed using slack time. This technique has improved the life time of the mobile systems by clock gating method, considered energy and using slack time. As an results, the proposed algorithm reduce average power saving up to 4% comparing to not apply processor in mobile system.

• Journal of Information Processing Systems
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• v.9 no.1
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• pp.41-52
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• 2013

One of the obstacles preventing the Zigbee protocol from being widely used is the excessive power consumption of Zigbee devices in low bandwidth and low power requirement applications. This paper proposes a protocol that resolves the power efficiency problem. The proposed protocol reduces the power consumption of Zigbee devices in beacon-enabled networks without increasing the time taken by Zigbee peripherals to communicate with their coordinator. The proposed protocol utilizes a beacon control mechanism called a "sleep pattern," which is updated based on the previous event statistics. It determines exactly when Zigbee peripherals wake up or sleep. A simulation of the proposed protocol using realistic parameters and an experiment using commercial products yielded similar results, demonstrating that the protocol may be a solution to reduce the power consumption of Zigbee devices.