• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1197-1200
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• 2003

This paper presents A/D converter for the signal processing of infrared sensor and CMOS image sensor. The A/D converter designed in a 0.25um CMOS process provides a resolution of 10bits at a sampling rate of 50MS/s while dissipating 67mW at 2.5V supply voltage. This A/D converter is based on a pipeline architecture in which the number of bits converted per stage and the stage number are optimized to achieve the desired linearity and reduce power consumption as well. Simulation results show that the A/D converter using 1.5bit per stage MDAC with switched capacitors and dynamic comparators efficiently reduces the power consumption.

• International journal of advanced smart convergence
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• v.1 no.2
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• pp.12-15
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• 2012

Energy costs for operating and cooling computing resources in Cloud infrastructure have increased significantly up to the point where they would surpass the hardware purchasing costs. Thus, reducing the energy consumption can save a significant amount of management cost. One of major approach is removing hardware over-provisioning. In this paper, we propose a technique that facilitates power saving through reducing resource over provisioning based on virtualization technology. To this end, we use dynamic workload shaping to reschedule and redistribute job requests considering overall power consumption. In this paper, we present our approach to shape workloads dynamically and distribute them on virtual machines and physical machines through virtualization technology. We generated synthetic workload data and evaluated it in simulating and real implementation. Our simulated results demonstrate our approach outperforms to when not using no workload shaping methodology.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.1
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• pp.25-32
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• 2014

In this paper, we proposed a partial-way set associative cache memory with an effective memory access time and low energy consumption. In the proposed set-associative cache memory, it is allowed to access only a 2-ways among 4-way at a time. Choosing ways to be accessed is made dynamically via the least significant two bits of the tag. The chosen 2 ways are sequentially accessed by the way selection bits that indicate the most recently referred way. Therefore, each entry in the way has an additional bit, that is, the way selection bit. In addition, instead of the 4-way LRU or FIFO algorithm, we can utilize a simple 2-way replacement policy. Simulation results show that the energy*delay product can be reduced by about 78%, 14%, 39%, and 15% compared with a 4-way set associative cache, a sequential-way cache, a way-tracking cache, and a way cache respectively.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.6
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• pp.1301-1308
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• 2012

In this paper, the low-power clock generator synchronized with the AC power signal using the adiabatic dynamic CMOS logic (ADCL) buffer is proposed for adiabatic logics. To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the ADCL, the clock signal of logic circuits should be synchronized with the AC power source. The clock signal for an adiabatic charging and discharging with the AC power signal was generated with the designed Schmitt trigger circuit and ADCL frequency divider using the ADCL buffer. From the simulation result, the power consumption of the proposed clock generator was estimated with approximately 1.181uW and 37.42uW at output 3kHz and 10MHz respectively.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1081-1084
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• 1998

In this paper, we propose the bus coding technique for low power consumption. For CMOS circuit most power is dissipated as dynamic power for charging and discharging node capacitances.Though the I/O and bus are likely to have the very large capacitances associated with them and dissipate much of the power dissipated by an IC, they have little beenthe special target for power reduction. The conventional Bus-Invert coding method can't decrease the peak power dissipation by 50% because the additional invert signal line can invoke a transition at the time when Bus-Invert coding isn't used to code original bus data. The proposed technique always constraints the Hamming distance between data transferred sequentially to be below the half of the bus width, and thus decrease the I/O peak power dissipation and the I/O average power dissipation.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.5
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• pp.431-437
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• 2012

PV simulators are essential equipment for testing power conditioning systems (PCS) which are one of an important part in PV generator systems, for testing before shipment. High dynamic PV simulator is required since MPPT(Maximum Power Point Tracking) test procedure has been established by EN50530 regulation recently. Most high quality PV simulator prevailed in the market is linear type which however has low efficiency. This paper proposes design guide lines for the power stage and LCL type filter cooperating with a switching mode PV simulator that shows high efficiency and very low power consumption. Proposed theory is verified by experiment.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.20 no.12
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• pp.775-780
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• 2008

A dynamic model to simulate LNG reliquefaction process has been developed. The model was applied to two candidate cycles for LNG reliquefaction process, which are Reverse Brayton and Claude cycles. The simulation was intended to simulate the pilot plant under construction for operation of the two cycles and evaluate their feasibility. According to the simulation results, both satisfy control requirements for safe operation of brazed aluminum plate-fin type heat exchangers. In view of energy consumption, the Reverse Brayton cycle is more efficient than the Claude cycle. The latter has an expansion valve in addition to the common facilities sharing with the Reverse Brayton cycle. The expansion valve is a main cause to the efficiency loss. It generates a significant amount of entropy associated with its throttling and increases circulation flow rates of the refrigerant and power consumption caused by its leaking resulting in lowered pressure ratio. It is concluded that the Reverse Brayton cycle is more efficient and simpler in control and construction than the Claude cycle.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.137-147
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• 2008

Recently, Power and thermal management are becoming major concerns in computer system design. The energy efficiency is an important attribute of the mobile and embedded systems. Today's powerful mobile processors needs more energy and longer battery life. Many research has been focused to reduce energy consumption for the mobile processors.In this paper, performance monitoring system for the Power-management techniques is implemented for Intel's XScale microarchitecture-based Marvell PXA320 processor on Windows CE platform. It also provides software interface for changing DVFS configuration. Performance and power consumption are measured for benchmark programs through performance counter value and voltage/current measurements on LabVIEW platform. By using the developed monitoring system, it is possible for dynamic power management to track processor's workload and to determine the actual power consumption.

• Journal of Korea Multimedia Society
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• v.8 no.8
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• pp.1042-1050
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• 2005

This paper proposed a novel low-power video decoding scheme for mobile multimedia communication. In general, there are quite a large number of non-coded blocks in the encoded bitstream where all quantized DCT coefficients are truncated into zero. When the number of the non-coded blocks are known at the start of frame decoding, the amount of computation reduction can be precisely estimated for frame decoding. When the computation reduces, the operation speed and the corresponding supply voltage of VLSI circuits in the decoder also reduce, thus thus power consumption also reduces. In the proposed scheme, the number of the non-coded blocks is stored in the frame header of the encoded bitstream, and the decoder efficiently reduces the power consumption exploiting this information. Simulation results show that the proposed scheme reduces the power consumption to about 1/20.

• International Journal of Ocean Engineering and Technology Speciallssue:Selected Papers
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• v.5 no.1
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• pp.46-52
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• 2002

A robust nonlinear observer, utilizing the sliding mode concept, is developed for the dynamic positioning of ships. The observer provides the estimates of linear velocities of the ship and bias from slowly varying environmental loads. It also filters out wave frequency motion to avoid wear of actuators and excessive fuel consumption. The main advantage of the proposed observer is in its robustness. Especially, the observer structure with a saturation function makes the proposed observer robust against neglected nonlinearties, disturbances and uncertainties. Since the mathematical model of DP ships is difficult to obtain and includes uncertainties and disturbances, it is very important for the observer to be robust. A nonlinear output feedback controller is derives based on the developed observer using the observer backstepping technique, and the global stability of the observer and control law is shown by Lyapunov stability theory.. A set of simulation was carried out to investigate the performance of the proposed observer for dynamic positioning of ships.