• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.37-40
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• 2003

The 1.63㎓, 2.33㎓ dual-band PLL frequency synthesizer has been developed for applications to the miniature repeater. The miniature dual-band repeater will be used at shopping mall, basements and underground parking lots. The in-loop 1.63㎓, 2.33㎓ dual-band PLL frequency synthesizer has been developed by designing Si BJT VCO and PLL loop circuits with Colpitts. The prototype of 1.63㎓, 2.33㎓ dual-band PLL frequency synthesizer of size 19${\times}$19${\times}$8(mm) has shown operating frequencies of 1.63㎓, 2.33㎓ ranges, RF output of 1dBm(PCS), 1dBm(IMT-2000), phase noise of -100 dBc/Hz(PCS), -95dBc/Hz(IMT-2000) at 10KHz offset, harmonics suppression of -24dB c(PCS), -15dBc(IMT-2000).

• Journal of Power Electronics
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• v.11 no.4
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• pp.456-463
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• 2011

Grid-connected converters have widely adopted LCL filters to acquire high harmonic suppression. However, the LCL filter increases the system order so that the design of the system stability would be complicated. Recently, sole-loop control strategies have been used for grid-connected converters with L or LC filters. But if the sole-loop control is directly transplanted to grid-connected converters with LCL filters, the systems may be unstable. This paper presents a novel dual-loop power control strategy composed of a power outer loop and a current inner loop. The outer loop regulates the grid-connected power. The inner loop improves the system stability margin and suppresses the resonant peak caused by the LCL filter. To obtain the control variables, a single-phase current detection is proposed based on PQ theory. The system transfer function is derived in detail and the influence of control gains on the system stability is analyzed with the root locus. Simulation and experimental results demonstrate the feasibility of the proposed control.

• Journal of Advanced Navigation Technology
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• v.16 no.1
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• pp.27-34
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• 2012

In this paper, Coplanar waveguide(CPW)-fed slot loop antenna, which is applicable to the dual band(2.4GHz~2.4835GHz, 5.15GHz~5.825GHz) for the wireless LAN, is proposed. In order to miniaturize the proposed antenna, slot loop is bent by meandering. The resonant frequencies in the required dual band are adjusted by variation of the resonant length of slot loop as well as slot width. In particular, use of capacitive coupling CPW feed provides impedance matching without a seperate matching circuit, because the amount of electromagnetic coupling can be controlled by the offset between feed and radiator. As a result, it has been observed that the proposed antenna satisfies not only the required return loss(${\leq}10dB$) but also has high efficiency(${\geq}80%$) over the whole frequency band. In order to check the validity of the proposed antenna, some simulated results for return loss and radiation pattern are presented in comparison with the measured results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.912-920
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• 2003

This paper is about the design of a small wide-band slot loop antenna, which consists of dual offset-fed and rectangular loop within the slot on a substrate. The proposed antenna is a novel structure generating a multi-resonances due to three geometrical resonance structures. The impedance matching of this antenna can be accomplished by changing the offset position of dual-fed at resonance frequencies. In this experiment, the slot of a fabricated antenna has a center frequency of 6.755㎓, 12.5mm${\times}$50mm in size and the rectangular loop has 10.5mm${\times}$27.5mm in size. The measured result is fractional bandwidth 63.21% with VSWR 2:1, which is agreed with the simulated result within 5% of error, and the maximum antenna gain is 7.42㏈i.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.899-905
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• 2017

This paper presents a reference-less dual loop clock and data recovery (CDR) circuit that supports a data rate of 2.496 Gb/s for the mobile industry processor interface (MIPI) M-PHY. An adaptive loop bandwidth scheme is used to implement the fast lock time maintaining a low time jitter. To this scheme, the proposed CDR consists of two loops for a frequency locked loop and a phase locked loop. The proposed 2.496 Gb/s reference-less dual loop CDR is designed using a 65 nm CMOS process with 1.2 V supply voltage. The simulated peak-to-peak jitter of output clock is 9.26 ps for the input data of 2.496 Gb/s pseudo-random binary sequence (PRBS) 15. The active area and power consumption of the implemented CDR are $470{\times}400{\mu}m^2$ and 6.49 mW, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.8 s.99
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• pp.783-789
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• 2005

In this paper, a novel design and implementation of a dual-band directional coupler based on RF IPD(Integrated Passive Device)-on-glass technology is proposed, which can be adopted in GSM/GPRS cellular phones for closed loop power control at the output of the power amplifier. The proposed coupler has a compensation capacitor to improve the directivity, and was designed using a new diplexing structure to minimize the cross-band isolation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.2
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• pp.245-251
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• 2011

In this paper, dual-band bandpass filter by using Pseudo-Interdigital Stepped-Impedance Resonator(PI-SIR) and Open-Loop Ring Resonator(OLRR) is proposed. The first passband and second passband are formed by PI-SIR and the second passband is reinforced by an OLRR. In a PI-SIR the first band and second band are easily and exactly adjusted by characteristic impedance ratio and electrical length ratio. The proposed design method may be confirmed to be useful from fabricated and measured results for dual-band bandpass filter operated at 2.45 GHz and 5.8 GHz.

• Proceedings of the KIEE Conference
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• 1996.07a
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• pp.262-264
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• 1996

This paper presents a new dual loop control using novel vector phase locked loop(VP-PLL) for a high power static var compensator(SVC) with three-level GTO voltage source inverter(VSI). Through circuit DQ-transformation, a simple dq-axis equivalent circuit is obtained. From this, DC analysis is carried out to obtain maximum controllable phase angle ${\alpha}_{max}$ per unit current between the three phase source and the switching function of inverter, and AC open-loop transfer function is given. Because ${\alpha}_{max}$ becomes small in high power SVC, this paper proposes VP-PLL for more accurate $\alpha$-control. As a result, the overall control loop has dual loop structure, which consists of inner VP-PLL for synchronizing the phase angle with source and outer Q-loop for compensating reactive power of load. Finally, the validity of the proposed control method is verified through the experimental results.

• Journal of the Optical Society of Korea
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• v.20 no.2
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• pp.300-304
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• 2016

A dual loop optoelectronic oscillator (OEO) based on an acousto-optic modulator (AOM) for single mode operation with an acousto-optic delay line is demonstrated in this paper. When the OEO operates, the free spectral range is a function of the total loop length of the OEO, which is mainly dependent on the propagation time of the acoustic wave in the AOM. Due to the huge difference in the magnitude between the speed of light and the acoustic velocity in the AOM, the effective loop length converted to light-propagation length of the OEO increases to 3.8 km. With 150 MHz oscillation frequency, phase noise of -118 dBc/Hz at 10 kHz frequency offset, and -140 dBc/Hz at 200 kHz frequency offset, is achieved.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.520-527
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• 2016

A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a $0.18-{\mu}m$ CMOS process, occupies an active area of $0.19mm^2$ and operates over a wide frequency range of 0.15-1.5 GHz. The DLL dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps (effective pk-pk jitter = 16.5 ps) with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps.