• Title/Summary/Keyword: dual-core

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3D Digital Mockup Application of Cryogenic Butterfly Valve, LNG Carrier (DMU(Digital Mockup) 기법을 적용한 LNG 선박용 극저온 버터플라이 밸브 설계의 우수성 검증)

  • Lee, Dong-Hun;Kim, Duck-Eun;Kim, Soo-Young;Park, Gy-Young
    • Journal of the Society of Naval Architects of Korea
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    • v.43 no.5 s.149
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    • pp.611-618
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    • 2006
  • Recently, cryogenic butterfly valves for LNG carriers are actively developed by ship equipment companies. The dual core structure unlike usual butterfly valve has both translation and gyration motions of the disk of the valve assembly. Especially, the ship equipment companies can not have overcome 2D design method; in addition, even though 2 years of development has passed, the drawing cannot be secured. In this research, for the cryogenic butterfly valves and the product design, 3D design method was introduced and DMU(Digital Mockup) was applied to complement the problems in 2D design and investigate application possibility of 3D design method.

An Ultrasonic Positioning System Using Zynq SoC (Zynq-SoC를 이용한 초음파 위치추적 시스템)

  • Kang, Moon-Ho
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.66 no.8
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    • pp.1250-1256
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    • 2017
  • In this research, a high-performance ultrasonic positioning system is proposed to track the positions of an indoor mobile object. Composed of an ultrasonic sender (mobile object) and a receiver (anchor), the system employs three ultrasonic time-off-flights (TOFs) and trilateration to estimate the positions of the object with an accuracy of sub-centimeter. On the other hand, because ultrasonic waves are interfered by temperature, wind and various obstacles obstructing the propagation while propagating in air, ultrasonic pulse debounce technique and Kalman filter were applied to TOF and position calculation, respectively, to compensate for the interference and to obtain more accurate moving object position. To perform tasks in real time, ultrasonic signals are processed full-digitally with a Zynq SoC, and as a software design tool, Vivado IDE(integrated design environment) is used to design the whole signal processing system in hierarchical block diagrams. And, a hardware/software co-design is implemented, where the digital circuit portion is designed in the Zynq's fpga and the software portion is c-coded in the Zynq's processors by using the baremetal multiprocessing scheme in which the c-codes are distributed to dual-core processors, cpu0 and cpu1. To verify the usefulness of the proposed system, experiments were performed and the results were analyzed, and it was confirmed that the moving object could be tracked with accuracy of sub-cm.

Chalcones as Novel Non-peptidic μ-Calpain Inhibitors

  • Lee, Eun-Young;Jang, In-Hye;Shin, Min-Jung;Cho, Hee-Ju;Kim, Jung-Sook;Eom, Ji-Eun;Kwon, Young-Joo;Na, Young-Hwa
    • Bulletin of the Korean Chemical Society
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    • v.32 no.9
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    • pp.3459-3464
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    • 2011
  • In order to extend the scaffold of non-peptidic calpain inhibitor, we have designed and synthesized 14 chalcone derivatives categorized into two groups based on their structures. Compounds 7 ($IC_{50}=16.67{\pm}0.42{\mu}M$) and 8 ($IC_{50}=16.92{\pm}0.14{\mu}M$) in group A were most selective ${\mu}$-calpain inhibitor over cathepsins B and L. On the other hand, compound 14 possessing furan ring exhibited inhibitory activities for ${\mu}$-calpain ($IC_{50}=15.39{\pm}1.34{\mu}M$) as well as cathepsin B ($IC_{50}=20.59{\pm}1.35{\mu}M$). The results discovered implicated that chalcone analogues possessing proper size and functional groups can be a potential lead core for selective non-peptidic ${\mu}$-calpain inhibitor. Furthermore, dual inhibitors for ${\mu}$-calpain and cathepsin B can also be developed from chalcones by elaborate structure manipulation.

A Study on the Development of a Cantilever & Swing-Type Fast Tool Servo with Rotational Moment Hinge Design (회전모멘트 힌지 설계에 따른 캔틸레버형 횡방향 구동 Fast Tool Servo 연구 개발에 관한 고찰)

  • Lee, Seung Jun;Jeong, Jae Ho
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.19 no.8
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    • pp.43-49
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    • 2020
  • The growth of the AR/VR market due to the advent of the 4th Industrial Revolution begins with the development of the display industry. The development of OLED and flexible displays is further accelerated by the development of R2R technology. Micro-processing technology using a fast tool servo (FTS), the core technology in R2R processes, is making technological progress in increasingly diverse ways. This paper proposes a method to develop an FTS for horizontal driving and presents this method through experiments and analyses. To develop a swing-type FTS based on a seesaw motion, a rotational moment hinge structure was designed for each type, and research was conducted to determine an effective design method. A cantilever-based swing-type FTS was developed in two variations: one with single-side hinges and another with dual-side hinges. The parameters in the design of the swing-type FTS are rotational moment, natural frequency, and material selection. In conclusion, an FTS with a single-side hinge demonstrates the high performance required for micro processing.

Short-circuit Analysis by the Application of Control Signal of Power Converter to the Inductive Fault Current Limiter

  • Ahn, Min-Cheol;Hyoungku Kang;Bae, Duck-Kweon;Minseok Joo;Park, Dong-Keun;Lee, Sang-Jin;Ko, Tae-Kuk
    • Progress in Superconductivity and Cryogenics
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    • v.6 no.2
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    • pp.25-28
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    • 2004
  • Three-phase inductive superconducting fault current limiter (SFCL) with DC reactor rated on 6.6 $KV_{rms}/200 A_{rms}$ has been developed in Korea. This system consists of one DC reactor, AC/DC power converter, and a three-phase transformer, which is called magnetic core reactor (MCR). This paper deals with the short-circuit analysis of the SFCL. The DC reactor was the HTS solenoid coil whose inductance was 84mH. The power converter was performed as the dual-mode operation for dividing voltage between the rectifying devices. The short-term normal operation (1 see) and short-circuit tests (2∼3 cycles) of this SFCL were performed successfully. In regular short-circuit test, the fault current was limited as 30% of rated short-circuit current at 2 cycles after the fault. The experimental results have a very similar tendency to the simulation results. Using the technique for the fault detection and SCR firing control, the fault current limiting rate of the SFCL was improved. From this research, the parameters for design and manufacture of large-scale SFCL were obtained.

Improving cyclic behavior of multi-level pipe damper using infill or slit diaphragm inside inner pipe

  • Zahrai, Seyed Mehdi;Cheraghi, Abdullah
    • Structural Engineering and Mechanics
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    • v.64 no.2
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    • pp.195-204
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    • 2017
  • Analytical and experimental studies of the innovative pipe in pipe damper have been recently investigated by the authors. In this paper, by adding lead or zinc infill or slit diaphragm inside the inner pipe, it is tried to increase the equivalent viscous damping ratio improving the cyclic performance of the recently proposed multi-level control system. The damper consists of three main parts including the outer pipe, inner pipe and added complementary damping part. At first plastic deformations of the external pipe, then the internal pipe and particularly the added core and friction between them make the excellent multi-level damper act as an improved energy dissipation system. Several kinds of added lead or zinc infill and also different shapes of slit diaphragms are modeled inside the inner pipe and their effectiveness on hysteresis curves are investigated with nonlinear static analyses using finite element method by ABAQUS software. Results show that adding lead infill has no major effect on the damper stiffness while zinc infill and slit diaphragm increase damper stiffness sharply up to more than 10 times depending on the plate thickness and pipe diameter. Besides, metal infill increases the viscous damping ratio of dual damper ranging 6-9%. In addition, obtained hysteresis curves show that the multi-level control system as expected can reliably dissipate energy in different imposed energy levels.

Bounding Worst-Case DRAM Performance on Multicore Processors

  • Ding, Yiqiang;Wu, Lan;Zhang, Wei
    • Journal of Computing Science and Engineering
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    • v.7 no.1
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    • pp.53-66
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    • 2013
  • Bounding the worst-case DRAM performance for a real-time application is a challenging problem that is critical for computing worst-case execution time (WCET), especially for multicore processors, where the DRAM memory is usually shared by all of the cores. Typically, DRAM commands from consecutive DRAM accesses can be pipelined on DRAM devices according to the spatial locality of the data fetched by them. By considering the effect of DRAM command pipelining, we propose a basic approach to bounding the worst-case DRAM performance. An enhanced approach is proposed to reduce the overestimation from the invalid DRAM access sequences by checking the timing order of the co-running applications on a dual-core processor. Compared with the conservative approach, which assumes that no DRAM command pipelining exists, our experimental results show that the basic approach can bound the WCET more tightly, by 15.73% on average. The experimental results also indicate that the enhanced approach can further improve the tightness of WCET by 4.23% on average as compared to the basic approach.

Formation of Poly(ethylene glycol)-Poly($\varepsilon$-caprolactone) Nanoparticles via Nanoprecipitation

  • Lee, Jae-Sung;Hwang, Su-Jong;Lee, Doo-Sung;Kim, Sung-Chul;Kim, Duk-Joon
    • Macromolecular Research
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    • v.17 no.2
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    • pp.72-78
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    • 2009
  • Size control of therapeutic carriers in drug delivery systems has become important due to its relevance to biodistribution in the human body and therapeutic efficacy. To understand the dependence of particle size on the formation condition during nanoprecipitation method, we prepared nanoparticles from biodegradable, amphiphilic block copolymers and investigated the particle size and structure of the resultant nanoparticles according to various process parameters. We synthesized monomethoxy poly(ethylene glycol)-poly($\varepsilon$-caprolactone) block copolymer, MPEG-PCL, with different MPEG/PCL ratios via ring opening polymerization initiated from the hydroxyl end group of MPEG. Using various formulations with systematic change of the block ratio of MPEG and PCL, solvent choice, and concentration of organic phase, MPEG-PCL nanoparticles were prepared through nanoprecipitation technique. The results indicated that (i) the nanoparticles have a dual structure with an MPEG shell and a PCL core, originating from self-assembly of MPEG-PCL copolymer in aqueous condition, and (ii) the size of nanoparticles is dependent upon two sequential processes: diffusion between the organic and aqueous phases and solidification of the polymer.

Improved Bridgeless Interleaved Boost PFC Rectifier with Optimized Magnetic Utilization and Reduced Sensing Noise

  • Cao, Guoen;Kim, Hee-Jun
    • Journal of Power Electronics
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    • v.14 no.5
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    • pp.815-826
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    • 2014
  • An improved bridgeless interleaved boost power factor correction (PFC) rectifier to improve power efficiency and component utilization is proposed in this study. With combined conventional bridgeless PFC circuit and interleaved technology, the proposed rectifier consists of two interleaved and magnetic inter-coupling boost bridgeless converter cells. Each cell operates alternatively in the critical conduction mode, which can achieve the soft-switching characteristics of the switches and increase power capacity. Auxiliary blocking diodes are employed to eliminate undesired circulating loops and reduce current-sensing noise, which are among the serious drawbacks of a dual-boost PFC rectifier. Magnetic component utilization is improved by symmetrically coupling two inductors on a unique core, which can achieve independence from each other based on the auxiliary diodes. Through the interleaved approach, each switch can operate in the whole line cycle. A simple control scheme is employed in the circuit by using a conventional interleaved controller. The operation principle and theoretical analysis of the converter are presented. A 600 W experimental prototype is built to verify the theoretical analysis and feasibility of the proposed rectifier. System efficiency reaches 97.3% with low total harmonic distortion at full load.

Two-Level Tries: A General Acceleration Structure for Parallel Routing Table Accesses

  • Mingche, Lai;Lei, Gao
    • Journal of Communications and Networks
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    • v.13 no.4
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    • pp.408-417
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    • 2011
  • The stringent performance requirement for the high efficiency of routing protocols on the Internet can be satisfied by exploiting the threaded border gateway protocol (TBGP) on multi-cores, but the state-of-the-art TBGP performance is restricted by a mass of contentions when racing to access the routing table. To this end, the highly-efficient parallel access approach appears to be a promising solution to achieve ultra-high route processing speed. This study proposes a general routing table structure consisting of two-level tries for fast parallel access, and it presents a heuristic-based divide-and-recombine algorithm to solve a mass of contentions, thereby accelerating the parallel route updates of multi-threading and boosting the TBGP performance. As a projected TBGP, this study also modifies the table operations such as insert and lookup, and validates their correctness according to the behaviors of the traditional routing table. Our evaluations on a dual quad-core Xeon server show that the parallel access contentions decrease sharply by 92.5% versus the traditional routing table, and the maximal update time of a thread is reduced by 56.8 % on average with little overhead. The convergence time of update messages are improved by 49.7%.