• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.27-34
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• 2012

In this paper, the implementation of high throughput two-dimensional (2-D) $8{\times}8$ forward and inverse integer DCT transform for H.264 is presented. The forward and inverse transforms are represented using simple shift and addition operations. Matrix decomposition and matrix operation such as the Kronecker product and direct sum are used to reduce the computation complexity. The proposed design uses integer computations and does not use transpose memory and hence, the resource consumption is also reduced. The maximum operating frequency of the proposed pipelined architecture is 1.184 GHz, which achieves 25.27 Gpixels/sec throughput rate with the hardware cost of 44864 gates. High throughput and low hardware makes the proposed design useful for real time H.264/AVC high definition processing.

• Proceedings of the KSRS Conference
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• v.1
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• pp.7-10
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• 2006

Four programs, i.e. TRMM, ADEOS2, ASTER, and ALOS are going on in Japanese Earth Observation programs. TRMM and ASTER are operating well, and TRMM operation will be continued to 2009. ADEOS2 was failed, but AMSR-E on Aqua is operating. ALOS (Advanced Land Observing Satellite) was successfully launched on $24^{th}$ Jan. 2006. ALOS carries three instruments, i.e., PRISM (Panchromatic Remote Sensing Instrument for Stereo Mapping), AVNIR-2 (Advanced Visible and Near Infrared Radiometer), and PALSAR (Phased Array L band Synthetic Aperture Radar). PRISM is a 3 line panchromatic push broom scanner with 2.5m IFOV. AVNIR-2 is a 4 channel multi spectral scanner with 10m IFOV. PALSAR is a full polarimetric active phased array SAR. PALSAR has many observation modes including full polarimetric mode and scan SAR mode. After the unfortunate accident of ADEOS2, JAXA still have plans of Earth observation programs. Next generation satellites will be launched in 2008-2012 timeframe. They are GOSAT (Greenhouse Gas Observation Satellite), GCOM-W and GCOM-C (ADEOS-2 follow on), and GPM (Global Precipitation Mission) core satellite. GOSAT will carry 2 instruments, i.e. a green house gas sensor and a cloud/aerosol imager. The main sensor is a Fourier transform spectrometer (FTS) and covers 0.76 to 15 ${\mu}m$ region with 0.2 to 0.5 $cm^{-1}$ resolution. GPM is a joint project with NASA and will carry two instruments. JAXA will develop DPR (Dual frequency Precipitation Radar) which is a follow on of PR on TRMM. Another project is EarthCare. It is a joint project with ESA and JAXA is going to provide CPR (Cloud Profiling Radar). Discussions on future Earth Observation programs have been started including discussions on ALOS F/O.

• Journal of Positioning, Navigation, and Timing
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• v.6 no.4
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• pp.195-203
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• 2017

A 2U cube satellite called SNUGLITE has been developed by GNSS Research Laboratory in Seoul National University. Its main mission is to perform actual operation by mounting dual-frequency global positioning system (GPS) receivers. Its scientific mission aims to observe space environments and collect data. It is essential for a cube satellite to control an Earth-oriented attitude for reliable and successful data transmission and reception. To this end, an attitude estimation and control algorithm, Attitude Determination and Control System (ADCS), has been implemented in the on-board computer (OBC) processor in real time. In this paper, the Extended Kalman Filter (EKF) was employed as the attitude estimation algorithm. For the attitude control technique, the Linear Quadratic Gaussian (LQG) was utilized. The algorithm was verified through the processor in the loop simulation (PILS) procedure. To validate the ADCS algorithm in the ground, the experimental verification via a single axis Hardware-in-the-loop simulation (HILS) was used due to the simplicity and cost effectiveness, rather than using the 3-axis HILS verification (Schwartz et al. 2003) with complex air-bearing mechanism design and high cost.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.2
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• pp.72-75
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• 2012

In this paper, high-efficiency DC-AC converter is implemented for the wireless power transmission. The DC-AC converter is implemented by combining the oscillator and power amplifier. Because the conversion efficiency of wireless power transmitter is strongly affected by the efficiency of power amplifier, the high-efficiency power amplifier is implemented by using the Class-E amplifier structure. Also, because the output power of oscillator connected to the input stage of power amplifier is low, high-gain two-stages power amplifier using the drive amplifier is implemented to realize the high-output power DC-AC converter. The dual band harmonic suppression filter is implemented to suppress 2nd, 3rd harmonics of 13.56 MHz. The output power and conversion efficiency of DC-AC converter are 40 dBm and 80.2 % at the operation frequency of 13.56 MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.896-897
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• 2013

In recent years, logistics tracking Device using GSM & WCDMA to improve logistics efficiency are being extensively researched. The purpose of this paper is to examine the performance development antenna usable cargo container security transport. Antenna developed by study were optimized to match logistics environment apply to GSM & WCDMA dual frequency for monitering system. The measure of antenna have confirmation VSWR is 3:1 measured in return loss -10dB. Reliability of this antenna has been verified about GSM & WCDMA through test-operation between the south korea and Russia.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.255-260
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• 2001

This paper describes the design of the Register Controlled DLL(Delay-Locked Loop) that achieves fast locking and low Power consumption using a new locking algorithm. A fashion for a fast locking speed is that controls the two controller in sequence. The up/down signal due to clock skew between a internal and a external clock in phase detector, first adjusts a large phase difference in coarse controller and then adjusts a small phase difference in fine controller. A way for a low power consumption is that only operates one controller at once. Moreover the proposed DLL shows better jitter performance Because using the lock indicator circuit. The proposed DLL circuit is operated from 50MHz to 200MHz by SPICE simulation. The estimated power dissipation is 15mA at 200MHz in 3.3V operation. The locking time is within 7 cycle at all of operating frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.2
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• pp.268-275
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• 2014

In this paper, a dual-band circular ring monopole antenna with stub and ground slot for WLAN(Wireless Local Area Networks)/WiMAX(World interoperability for Microwave Access) applications. The proposed antenna is based on a planar monopole design, and composed of one circular ring of radiating patch, cross strip in circular ring, modified feed line, and two rectangular slot in the ground plane for triple-band operation. To obtain the optimized parameters, we used the simulator, Ansoft's High Frequency Structure Simulator(HFSS) and found the parameters that greatly effect antenna characteristics. Using the obtained parameters, the antenna is fabricated. The numerical and experiment results demonstrated that the proposed antenna satisfied the -10 dB impedance bandwidth requirement while simultaneously covering the WLAN and WiMAX bands. And characteristics of gain and radiation patterns are determined for WLAN/WiMAX application.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.49-56
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• 2004

The performance of the multiprocessor systems is limited by the several factors. The system performance is affected by the processor speed, memory delay, and interconnection network bandwidth/latency. By the evolution of semiconductor technology, off the shelf microprocessor speed breaks beyond GHz, and the processors can be scalable up to multiprocessor system by connecting through the interconnection networks. In this situation, the system performances are bound by the latencies and the bandwidth of the interconnection networks. SCI, Myrinet, and Gigabit Ethernet are widely adopted as a high-speed interconnection network links for the high performance cluster systems. Performance improvement of the interconnection network can be achieved by the bandwidth extension and the latency minimization. Speed up of the operation clock speed is a simple way to accomplish the bandwidth and latency betterment, while its physical distance makes the difficulties to attain the high frequency clock. Hence the system performance and scalability suffered from the interconnection network limitation. Duplicating the link of the interconnection network is one of the solutions to resolve the bottleneck of the scalable systems. Dual-ring SCI link structure is an example of the interconnection network improvement. In this paper, I propose a network topology and a transaction path algorism, which optimize the latency and the efficiency under the duplicated links. By the simulation results, the proposed structure shows 1.05 to 1.11 times better latency, and exhibits 1.42 to 2.1 times faster execution compared to the dual ring systems.

• Journal of Navigation and Port Research
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• v.33 no.10
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• pp.691-697
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• 2009

Hardware dedicated off-the-shelf maritime differential GPS RSIM lacks the open architecture to meet all the minimum maritime user requirements and to include future GNSS improvements after recapitalization. This paper carries out a study to replace existing hardware dedicated differential GPS RSIM with software differential GPS RSIM in order to make up the weak point of hardware dedicated off-the-shelf maritime differential GPS RSIM. In this paper, the architecture of software RSIM is proposed for maritime DGPS recapitalization. And the feasibility analysis of the proposed software differential GPS RSIM is performed as the first phase to realize the proposed architecture. For the feasibility analysis, the prototype RF module and DSP module are implemented with properties as wide RF bandwidth, high sampling frequency, and high speed transmission interface. This paper shows that the proposed architecture has the possibility of real time operation of software RSIM functionality onto the PC-based platform through the analysis of computation time. Finally, this paper verifies that the L1/L2 dual frequency software differential RSIM designed according to the proposed method satisfies the performance specifications set out in RTCM paper 221-2006-SC104-STD.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.21-31
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• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.