• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.8
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• pp.53-59
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• 2008

In this paper, a novel dual-band high-efficiency class-F power amplifier using the composite right/left-handed (CRLH) transmission lines (TLs) has been realized with one RF Si lateral diffusion metal-oxide-semiconductor field effect transistor (LDMOSFET). The CRLH TL can lead to metamaterial transmission line with the dual-band tuning capability. The dual-band operation of the CRLH TL is achieved by the frequency offset and the nonlinear phase slope of the CRLH TL for the matching network of the power amplifier. Because the control of the all harmonic components is very difficult in dual-band, we have managed only the second- and third-harmonics to obtain the high efficiency with the CRLH TL in dual-band. Also, the proposed power amplifier has been realized by using the harmonic control circuit for not only the output matching network, but also the input matching network for better efficiency. Two operating frequencies are chosen at 880 MHz and 1920 MHz in this work. The measured results show that the output power of 39.83 dBm and 35.17 dBm was obtained at 880 MHz and 1920 MHz, respectively. At this point, we have obtained the power-added efficiency (PAE) of 79.536 % and 44.04 % at two operation frequencies, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2265-2272
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• 2013

In this paper, a dual-band circular ring monopole antenna with stub and ground slot for is proposed WLAN(Wireless Local Area Networks) applications. The proposed antenna is based on a planar monopole design, and composed of one circular ring of radiating patches, and modified feed line, and rectangular slot in the ground plane for dual-band operation. To obtain the optimized parameters, we used the simulator, Ansoft's High Frequency Structure Simulator(HFSS) and found the parameters that effect antenna characteristics. Using the obtained parameters, the antenna is fabricated, and the return loss coefficient, gain, and radiation patterns are determined for WLAN application.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.74-75
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• 2016

Various types of microstrip antennas can be used for many applications in wireless communication systems. In this paper, we studied a design method for a broadband dual-fed stacked microstrip patch antenna. The impedance bandwidth is improved by adjusting the sizes of main radiating patch and parasitic patch, the distance between the patches, the length of inset feed line, etc. The antenna is designed by simulation for an operation in the frequency range of 2.3-2.7 GHz, and the antenna characteristics such as return loss, gain, radiation patterns are examined.

• Journal of IKEEE
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• v.23 no.1
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• pp.58-67
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• 2019

A design of an elliptic curve cryptography (ECC) processor that supports both pseudo-random curves and Koblitz curves over $GF(2^m)$ defined by the NIST standard is described in this paper. A finite field arithmetic circuit based on a word-based Montgomery multiplier was designed to support five key lengths using a datapath of fixed size, as well as to achieve a lightweight hardware implementation. In addition, Lopez-Dahab's coordinate system was adopted to remove the finite field division operation. The ECC processor was implemented in the FPGA verification platform and the hardware operation was verified by Elliptic Curve Diffie-Hellman (ECDH) key exchange protocol operation. The ECC processor that was synthesized with a 180-nm CMOS cell library occupied 10,674 gate equivalents (GEs) and a dual-port RAM of 9 kbits, and the maximum clock frequency was estimated at 154 MHz. The scalar multiplication operation over the 223-bit pseudo-random elliptic curve takes 1,112,221 clock cycles and has a throughput of 32.3 kbps.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.12
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• pp.16-21
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• 2007

In this paper, the dual-band voltage-controled oscillator (VCO) using the composite right/left-handed (CRLH) transmission line (TL) and the tunable negative resistance based on the fin diode is presented. It is demonstrated that the CRLH TL can lead to metamaterial transmission line with the dual-band tuning capability. The dual-band operation of the CRLH TL is achieved by the frequency offset and the phase slope of the CRLH TL, and the frequency ratio of the two operating frequencies can be a non-integer. Each frequency band of VCO has to operate independently, so we have used the tunable negative resistance based on the pin diode. When the forward bias has been into the pin diode, the phase noise of VCO is $-108.34\sim-106.67$ dBc/Hz @ 100 kHz in the tuning range, $2.423\sim2.597$ GHz, whereas when the reverse bias has been fed into the pin diode, that of VCO is $-114.16\sim-113.33$ dBc/Hz @ 100 kHz in the tuning range, $5.137\sim5.354$ GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.408-420
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• 2003

This paper describes a Delay Locked Loop (DLL) circuit having two advancements : 1) a dual loop operation for a wide lock-range and 2) programmable replica delays using antifuse circuitry and internal voltage generator for a post-package skew calibration. The dual loop operation uses information from the initial time-difference between reference clock and internal clock to select one of the differential internal loops. This increases the lock-range of the DLL to the lower frequency. In addition, incorporation with the programmable replica delay using antifuse circuitry and internal voltage generator allows for the elimination of skews between external clock and internal clock that occur from on and off-chip variations after the package process. The proposed DLL, fabricated on 0.16m process, operates over the wide range of 42MHz - 400MHz with 2.3v power supply. The measured results show 43psec peak-to-peak jitter and 4.71psec ms jitter consuming 52㎽ at 400MHz.

• KEPCO Journal on Electric Power and Energy
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• v.1 no.1
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• pp.1-8
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• 2015

When the line and switchgear of the substation system are disconnected, ferro-resonance can occur. This happens even if the capacitive reactance and inductive reactance are not equal, which are not common resonance conditions. Resonance conditions vary depending on the busbar configuration environment. Although the damping resistance method applying the existing saturable reactor to cope with ferro-resonance has been successfully applied on site, there can be loss of normal function during long-term operation. The reason is because the rise in the operating frequency of saturable reactors means the saturation number is increased. Therefore, it can no longer function as saturable reactor since the resistor having inadequate capacity is burned out. To address this problem, in this paper, an EMTP-based simulation test was performed by designing and applying a dual reactor method, which adds an extended divergence reactor to the 1st side of the VT. The test result confirms that when the divergence reactor is inserted, the voltage and current values obtained at the 1st side and 2nd side of the VT as well as current values of divergence reactor part were stabilized from the transient phenomena and return to normal values. When compared with existing measures, although this method is similar in adding having a reactor added to a system regarding ferro-resonance, it has the advantage of being able to prevent ferro-resonance in advance since the reactor is added before the system is saturated. In addition, because it does not use damping resistance, it can extend the equipment life and stabilize its operation. Therefore, there are a lot of differences in terms of its operating characteristics and achivement of goal between the conventional method and new divergence reactor method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1C
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• pp.113-122
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• 2010

In this paper, we propose a CP (Cyclic Prefix) detection based SSS (Secondary Synchronization Signal) detection method for initial cell search in 3GPP LTE (3rd Generation Partnership Project Long Term Evolution) FDD/TDD (Frequency Division Duplex/Time Division Duplex) dual mode downlink receiver. In general, a blind coherent SSS detection method which can detect SSS without CP detection is applied. However, coherent detection method caused performance degradation by channel compensation error at high speed environment because it uses estimated CFR (Channel Frequency Response) at PSS (Primary Synchronization Signal), and it can be more serious problem in TDD mode due to increased distance between PSS and SSS. Also blind detectionhas the drawback of high computational complexity. Therefore, we proposed a CP type pre-decision structure with non-coherent SSS detection which has stable operation in high speed channel environments for 3GPP LTE TDD mode as well as FDD mode, and can reduce computational complexity by applying CP detection before SSS detection. Simulation results show that the proposed method has stable operation for 3GPP LTE TDD/FDD dual mode downlink receiver in various channel environments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.819-825
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• 2016

In this paper, a phase locked loop structure with parallel dual loop which have a different bandwidth has been proposed. The bandwidths depending on transfer functions are obtained through dual loops. Two different bandwidths of each loop are used to suppress noise on the operating frequency range. The proposed phase locked loop has two different voltage controlled oscillator gains to control two different wide and narrow loop filters. Furthermore, it has the locking status indicator to achieve an accurate locking condition. The phase margin of $58.2^{\circ}$ for wide loop and $49.4^{\circ}$ for narrow loop is designed for stable operation and the phase margin of $45^{\circ}$ is maintained during both loops work together. It has been designed with a 1.8V 0.18um complementary metal oxide semiconductor (CMOS) process. The simulation results show that the proposed phase locked loop works stably and generates a target frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.63-64
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• 2013

In this paper, a design method for a dual dipole antenna for an operation in the frequency band of 470-806 MHz for indoor digital TV (DTV) is studied. The proposed antenna is composed of two planar dipoles connected by parallel strip line, and the antenna is fed by a microstrip line. By employing different lengths of dipoles, a broadband characteristics is obtained, and the antenna is size-reduced by bending both ends of the longer dipole. The effects of each parameters on the antenna performance are examined by simulation, and the parameters are optimized for the DTV use. A prototype antenna with optimized parameters for the indoor DTV use is fabricated on an FR4 substrate and tested experimentally. The experimental results show that the frequency band for a VSWR < 2 ranges 458-864 MHz (61.4%, bandwidth 406 MHz, 1.89:1), and it corresponds fairly well with the simulated band 448-868 MHz (63.8%, bandwidth 420 MHz, 1.94:1).