• Title/Summary/Keyword: dry-etching

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Growth of CdTe Solar Cells and Surface Texturing of Photonic devices

  • Kim, Ji-Hyeon
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.08a
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    • pp.27-27
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    • 2010
  • 결정성과 전하 이동도가 우수한 CdTe 박막을 증착하기 위하여 근접승화법(CSS), chemical spraying법, 전착(electrodeposition)법, screen printing법, 화학기상증착(MOCVD)법 및 sputtering법등이 응용되고 있으며 이들 방법은 각기 다양한 장단점을 가지고 있다. CdTe 태양전지를 성장시키는 다양한 방법 중에서 본 발표는 CBD를 이용한 CdS와 CSS를 이용한 CdTe 박막 태양전지를 성장하는 방법을 포함한다. 다양한 조건에서 성장된 박막의 물성과 CdCl2와 열처리를 통한 성능개선에 대해 발표할 예정이다. 또한, 공기의 index와 박막의 index 차이가 크기 때문에, escape cone의 angle이 매우 작고, 박막의 경우 표면이 비교적 평평하기 때문에, 광소자(LED와 Solar Cell)는 표편 텍스처링이 성능을 향상시키기 위해 필요하다. Natural Lithography, Wet-etching, Dry-etching, index-grading을 이용하여, LED와 태양전지에서 uniform하고 대면적에 적용가능한 표면 택스처링 방법에 대해 발표할 예정이다.

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Effect of corrugation structure and shape on the mechanical stiffness of the diaphragm

  • Kim, Junsoo;Moon, Wonkyu
    • Journal of Sensor Science and Technology
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    • v.30 no.5
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    • pp.273-278
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    • 2021
  • Here, we studied the change in the mechanical stiffness of a diaphragm according to the corrugation pattern. The diaphragm consists of a silicon oxide and nitride double layer; a corrugation pattern was formed by dry etching, and the diaphragm was released by wet etching. The fabrication of the thin film was verified using focused ion beam and scanning electron microscopy images. The mechanical stiffness of the diaphragm was obtained by measuring the surface vibration using a laser Doppler vibrometer while applying external sound pressure. Flat squares, diaphragms with square corrugations, and circular corrugation patterns were measured and compared. The stiffness of the diaphragm with a corrugation structure was found to be smaller than that without a corrugation structure; in particular, circular corrugation showed a better effect because of the high symmetry. Furthermore, the effect of corrugation was theoretically predicted. The proposed corrugated diaphragm showed comparable flexibility with the state-of-the-art MEMS microphone diaphragm.

Continuous Process for the Etching, Rinsing and Drying of MEMS Using Supercritical Carbon Dioxide (초임계 이산화탄소를 이용한 미세전자기계시스템의 식각, 세정, 건조 연속 공정)

  • Min, Seon Ki;Han, Gap Su;You, Seong-sik
    • Korean Chemical Engineering Research
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    • v.53 no.5
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    • pp.557-564
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    • 2015
  • The previous etching, rinsing and drying processes of wafers for MEMS (microelectromechanical system) using SC-$CO_2$ (supercritical-$CO_2$) consists of two steps. Firstly, MEMS-wafers are etched by organic solvent in a separate etching equipment from the high pressure dryer and then moved to the high pressure dryer to rinse and dry them using SC-$CO_2$. We found that the previous two step process could be applied to etch and dry wafers for MEMS but could not confirm the reproducibility through several experiments. We thought the cause of that was the stiction of structures occurring due to vaporization of the etching solvent during moving MEMS wafer to high pressure dryer after etching it outside. In order to improve the structure stiction problem, we designed a continuous process for etching, rinsing and drying MEMS-wafers using SC-$CO_2$ without moving them. And we also wanted to know relations of states of carbon dioxide (gas, liquid, supercritical fluid) to the structure stiction problem. In the case of using gas carbon dioxide (3 MPa, $25^{\circ}C$) as an etching solvent, we could obtain well-treated MEMS-wafers without stiction and confirm the reproducibility of experimental results. The quantity of rinsing solvent used could be also reduced compared with the previous technology. In the case of using liquid carbon dioxide (3 MPa, $5^{\circ}C$, we could not obtain well-treated MEMS-wafers without stiction due to the phase separation of between liquid carbon dioxide and etching co-solvent(acetone). In the case of using SC-$CO_2$ (7.5 Mpa, $40^{\circ}C$), we had as good results as those of the case using gas-$CO_2$. Besides the processing time was shortened compared with that of the case of using gas-$CO_2$.

Selective Dry Etching of GaAs/AlGaAs Layer for HEMT Device Fabrication (HEMT 소자 제작을 위한 GaAs/AlGaAs층의 선택적 건식식각)

  • 김흥락;서영석;양성주;박성호;김범만;강봉구;우종천
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.28A no.11
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    • pp.902-909
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    • 1991
  • A reproducible selective dry etch process of GaAs/AlGaAs Heterostructures for High Electron Mobility Transistor(HEMT) Device fabrication is developed. Using RIE mode with $CCl_{2}F_{2}$ as the basic process gas, the observed etch selectivity of GaAs layer with respect to GaAs/$Al_{0.3}Ga_{0.7}$As is about 610:1. Severe polymer deposition problem, parialy generated from the use of $CCl_{2}F_{2}$ gas only, has been significantly reduced by adding a small amount of He gas or by $O_{2}$ plasma ashing after etch process. In order to obtain an optimized etch process for HEMT device fabrication, we com pared the properties of the wet etched Schottky contact with those of the dry etched one, and set dry etch condition to approach the characteristics of Schottky diode on wet etched surface. By applying the optimized etch process, the fabricated HEMT devices have the maximum transconductance $g_{mext}$ of 224 mS/mm, and have relatively uniform distribution across the 2inch wafer in the value of 200$\pm$20mS/mm.

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Plasma Charge Damage on Wafer Edge Transistor in Dry Etch Process (Dry Etch 공정에 의한 Wafer Edge Plasma Damage 개선 연구)

  • Han, Won-Man;Kim, Jae-Pil;Ru, Tae-Kwan;Kim, Chung-Howan;Bae, Kyong-Sung;Roh, Yong-Han
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2007.06a
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    • pp.109-110
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    • 2007
  • Plasma etching process에서 magnetic field 영향에 관한 연구이다. High level dry etch process를 위해서는 high density plasma(HDP)가 요구된다. HDP를 위해서 MERIE(Magnetical enhancement reactive ion etcher) type의 설비가 사용되며 process chamber side에 4개의 magnetic coil을 사용한다. 이런 magnetic factor가 특히 wafer edge부문에 plasma charging에 의한 damage를 유발시키고 이로 인해 device Vth(Threshold voltage)가 shift 되면서 제품의 program 동작 문제의 원인이 되는 것을 발견하였다. 이번 연구에서 magnetic field와 관련된 plasma charge damage를 확인하고 damage free한 공정조건을 확보하게 되었다.

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Research on Fabrication of Silicon Lens for Optical Communication by Photolithography Process (포토리소그래피를 통한 광통신용 실리콘 렌즈 제작 및 특성 연구)

  • Park, Junseong;Lee, Daejang;Rho, Hokyun;Kim, Sunggeun;Heo, Jaeyeong;Ryu, Sangwan;Kang, Sung-Ju;Ha, Jun-Seok
    • Journal of the Microelectronics and Packaging Society
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    • v.25 no.2
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    • pp.35-39
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    • 2018
  • In order to improve the coupling efficiency, a collimator lens that collects the light emitted from the laser diode at a wide angle to the core of the optical fiber is essential. Glass mold method using a mold is widely used as a collimator lens currently used. Although this method is inexpensive to produce, it is difficult to form precisely and quality problems such as spherical aberration. In this study, the precision of surface processing was improved by replacing the existing glass mold method with the semiconductor process, and the material of the lens was changed to silicon suitable for the semiconductor process. The semiconductor process consists of a photolithography process using PR and a dry etching process using plasma. The optical coupling efficiency was measured using an ultra-precision alignment system for the evaluation of the optical characteristics of the silicon lens. As a result, the optical coupling efficiency was 50% when the lens diameter was $220{\mu}m$, and the optical coupling property was 5% or less with respect to the maximum optical coupling efficiency in the lens diameter range of $210-240{\mu}m$.

Improvement of Light Extraction Efficiency of GaN-Based Vertical LED with Microlens Structure

  • Kwon, Eunhee;Kang, Eun Kyu;Min, Jung Wook;Lee, Yong Tak
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.08a
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    • pp.221-221
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    • 2013
  • Vertical LED (VLED) has been recognized as a way to obtain the high-power LED due to their advantages [1]. However, approximately 4% of the light generated from the active region is extracted, if the light extraction from side walls and back side is neglected because of Fresnel reflection (FR) and total internal reflection (TIR) [2,3]. In this study, the optical simulation of the VLED with the various microstructures was performed. Among them, the microlens having the diameter of 3 ${\mu}m$ and the height of 1.5 ${\mu}m$ shown the best result was chosen, and then, optimized microlens was formed on a GaN template using conventional semiconductor process. Various microstructures were proposed to improve the light extraction efficiency (LEE) of the VLED for the simulation. The LEE was simulated using LightTools based on a Monte Carlo ray tracing. The microstructures with hemisphere, cone, truncated and cylinder pattern having diameter of 3 ${\mu}m$ were employed on the top layer of the VLED respectively. The improvement of the LEE by using the microstructure is 87% for the hemisphere, 77% for the cone, 53% for the truncated, 21% for the cylinder, compared with the LEE of the flat surface at the reflectance of 85%. The LEE was increased by 88% at the height of 1.5 ${\mu}m$, compared with the LEE of the flat surface. We found that the microlens on the top layer is the most suitable for increasing the LEE. In order to apply the proposed microlens on n-GaN surface, we fabricated microlens on a GaN template. A photoresist array having hexagonal-closed packed microlens was fabricated on the GaN template. Then, optimization of etching the GaN template was performed using a dry etching process with ICP-RIE. The dry etching carried out using a gas mixture of Cl2 and Ar, each having a flow rate of 16 sccm and 10 sccm, respectively with RF power of 50 W, ICP power of 900 W and chamber pressure of 2 mTorr was the optimum etching condition as shown in Fig. 2(a).

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Efficient Shadow-Test Algorithm for the Simulation of Dry Etching and Topographical Evolution (건식 식각 공정 시뮬레이션을 위한 효율적인 그림자 테스트 알고리즘과 토포그래피 진화에 대한 연구)

  • Kwon, Oh-Seop;Ban, Yong-Chan;Won, Tae-Young
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.36D no.2
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    • pp.41-47
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    • 1999
  • In this paper, we report 3D-simulations of a plasma etching process by employing cell-removal algorithm takes into account the mask shadow effect os well as spillover errors. The developed simulator haas an input interface to take not only an analytic form but a Monte Carlo distribution of the ions. The graphic user interface(GUI) was also built into the simulator for UNIX environment. To demonstrate the capability of 3D-SURFILER(SURface proFILER), we have simulated for a typical contact hole structure with 36,000($30{\times}40{\times}30$) cells, which takes about 20 minutes with 10 Mbytes memory on sun ultra sparc 1. as an exemplary case, we calculated the etch profile during the reactive ion etching(RIE) of a contact hole wherein the aspect ratio is 1.57. Furthermore, we also simulated the dependence of a damage parameter and the evolution of topography as a function of the chamber pressure and the incident ion flux.

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Development of High Performance Massively Parallel Processing Simulator for Semiconductor Etching Process (건식 식각 공정을 위한 초고속 병렬 연산 시뮬레이터 개발)

  • Lee, Jae-Hee;Kwon, Oh-Seob;Ban, Yong-Chan;Won, Tae-Young
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.36D no.10
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    • pp.37-44
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    • 1999
  • This paper report the implementation results of Monte Carlo numerical calculation for ion distributions in plasma dry etching chamber and of the surface evolution simulator using cell removal method for topographical evolution of the surface exposed to etching ion. The energy and angular distributions of ion across the plasma sheath were calculated by MC(Monte Carlo) algorithm. High performance MPP(Massively Parallel Processing) algorithm developed in this paper enables efficient parallel and distributed simulation with an efficiency of more than 95% and speedup of 16 with 16 processors. Parallelization of surface evolution simulator based on cell removal method reduces simulation time dramatically to 15 minutes and increases capability of simulation required enormous memory size of 600Mb.

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A Study on the Design and Fabrication of the Planar Light Waveguide type $2\times32$ Optical Coupler (평면도파로형 $2\times32$ 광커플러의 설계와 제작에 관한 연구)

  • 신기수;최영복;류근호;문동찬
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.12B
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    • pp.2335-2341
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    • 1999
  • The $2\times32$ coupler consists of Mach-Zehnder interferometer and Y branch coupler. For the designs of this coupler, three dimensional rectangular core waveguide decomposed to two-dimensional structure by the effective index method. To optimize the waveguide structure, the confinement factor was investigated with two-dimensional finite difference Beam Propagation Method. The $2\times32$ coupler fabricated by simulation with height between Mach-Zehnder arms, H=$43.6\mu\textrm{m}$(path difference $0.668\mu\textrm{m}$) was showed best characteristics. In the results of dry etching of core layer, the etching rate of core layer was above 2600${\AA}$/min, the etching ratio of SiO2 to Al mask was 30:1 and the uniformity of etching was $\pm$5%. The maximum insertion loss and the uniformity of $2\times32$ coupler were below 19.2dB, 2dB respectively.

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