• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.2
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• pp.79-83
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• 2016

This research was analyzed thermal characteristics that was appointed disadvantage when smart LED driver ICs was packaged and we applied extracted thermal characteristics for optimal layout design. We confirmed reliability of smart LED driver ICs package without additional heat sink. If the package is not heat sink, we are possible to minimize package. For extracting thermal loss due to overshoot current, we increased driver current by two and three times. As a result of experiment, we obtained 22 mW and 49.5 mW thermal loss. And we obtained optimal data of 350 mA driver current. It is important to distance between power MOSFET and driver ICs. If thhe distance was increased, the temperature of package was decreased. And so we obtained optimal data of 3.7 mm distance between power MOSFET and driver ICs. Finally, we fabricated real package and we analyzed the electrical characteristics. We obtained constant 35 V output voltage and 80% efficiency.

• Transactions on Electrical and Electronic Materials
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• v.18 no.2
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• pp.59-61
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• 2017

This research was analyzed thermal characteristics that was appointed disadvantage when smart LED driver ICs was packaged and we applied extracted thermal characteristics for optimal layout design. We confirmed reliability of smart LED driver ICs package without additional heat sink. If the package is not heat sink, we are possible to minimize package. For extracting thermal loss due to overshoot current, we increased driver current by two and three times. As a result of experiment, we obtained 22 mW and 49.5 mW thermal loss. And we obtained optimal data of 350 mA driver current. It is important to distance between power MOSFET and driver ICs. If the distance was increased, the temperature of package was decreased. And so we obtained optimal data of 3.7 mm distance between power MOSFET and driver ICs. Finally, we fabricated real package and we analyzed the electrical characteristics. We obtained constant 35 V output voltage and 80% efficiency.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.3
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• pp.131-134
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• 2016

This research was analyzed thermal characteristics that was appointed disadvantage when smart LED driver ICs was packaged and we applied extracted thermal characteristics for optimal layout design. We confirmed reliability of smart LED driver ICs package without additional heat sink. If the package is not heat sink, we are possible to minimize package. For extracting thermal loss due to overshoot current, we increased driver current by two and three times. As a result of experiment, we obtained 22 mW and 49.5 mW thermal loss. And we obtained optimal data of 350 mA driver current. It is important to distance between power MOSFET and driver ICs. If thhe distance was increased, the temperature of package was decreased. And so we obtained optimal data of 3.7 mm distance between power MOSFET and driver ICs. Finally, we fabricated real package and we analyzed the electrical characteristics. We obtained constant 35 V output voltage and 80% efficiency.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.2
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• pp.75-78
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• 2016

This research was designed 700 level power MOSFET for smart LED driver ICs package. And we analyzed electrical characteristics of the power MOSFET as like breakdown voltage, on-resistance and threshold voltage. Because this research is important optimal design for smart LED ICs package, we designed power MOSFET with design and process parameter. As a result of this research, we obtained $60{\mu}m$ N-drift layer depth, 791.29 V breakdown voltage, $0.248{\Omega}{\cdot}cm^2$ on resistance and 3.495 V threshold voltage. We will use effectively this device for smart LED driver ICs package.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.688-696
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• 2014

A slew-rate control method of LCD driver ICs is introduced to increase uniformity between adjacent driver ICs and reduce power consumption. The slew rate of every voltage follower is calibrated by a feedback algorithm during the non-displaying period. Under normal operation mode, the slew rate is dynamically controlled for improving power efficiency. Experimental results show that the power consumption is reduced by 16% with a white pattern and by 10% with a black pattern, and display defects are successfully eliminated.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.6
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• pp.543-547
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• 2008

In the paper, we develop the ultrasonic bonding technique for LCD driver chips having small size and high pin-density. In general, the mounting technology for LCD driver ICs is a thermo-compression method utilizing the ACF (An-isotropic Conductive Film). The major drawback of the conventional approach is the long process time. It will be shown that the conventional ACF method based on thermo-compression can be remarkably enhanced by employing the ultrasonic bonding technique in terms of bonding time. The proposed approach is to apply the ultrasonic energy together with the thermo-compression methodology for the ACF bonding process. To this end, we design a bonding head that enables pre-heating, pressure and ultrasonic excitation. Through the bonding experiments mainly with LCD driver ICs, we present the procedures to select the best combination of process parameters with analysis. We investigate the effects of bonding pressure, bonding time, pre-heating temperature before bonding, and the power level of ultrasonic energy. The addition of ultrasonic excitation to the thermo-compression method reduces the pre-heating temperature and the bonding process time while keeping the quality bonding between the LCD pad and the driver IC. The proposed concept will be verified and demonstrated with experimental results.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.352-354
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• 2008

A 15.4" WXGA TFT-LCD, featuring integrated a-Si:H gate driver circuits and reduced data driver ICs, has been developed. To reduce number of data lines into 1/2 of conventional structure, the pixel array has been re-mapped with re-organized data signal. Unintended artificial effects such as flicker were removed by adopting the novel pixel array having a 'zigzag' map. To minimize the power consumption, a column inversion method was incorporated in the zigzag pixel array (Fig.1) without modifying the polarity map of conventional dot inversion method.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2008.10a
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• pp.105-107
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• 2008

LED driver is important for reliable LED lighting system. A variety of ICs for LED driver are supplied by almost all semiconductor company The types and performances are too diverse to collect proper IC and use efficiently. This paper classifies driver IC according to the usage for each application area and the circuit topology. Finally, the paper shows several representative ICs for main applications with notice of important performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.484-492
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• 2015

This paper proposes a PWM phase-shift circuit to make that the LED lighting system distributes the channel currents evenly for any number of LED strings by generating evenly phase-shifted PWM signals for multiple LED driver ICs. The evenly distributed channel currents reduce the peak current, the decoupling capacitor size, and EMI noise. The PWM phase-shift circuit makes an arbitrary degree of PWM phase-shift by using a resistor and a capacitor. It measures the RC delay once. It reduces the number of external resistors and capacitors by providing zero and 180 degree phase-shift modes requiring no resistor and capacitor. An LED driver IC with the PWM phase-shift circuit was fabricated with a $0.35{\mu}m$ BCDMOS process. The PWM phase-shift circuit receives a PWM signal of 50 Hz~20 kHz at $f_{CLK}=450kHz$ and it generates a $0{\sim}360^{\circ}$ phase-shifted PWM signal with $R=0{\sim}1.1M{\Omega}$ at C=1 nF and $f_{PWM}=1kHz$. The measured phase errors are 1.74~3.94% due to parasitic capacitances.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.923-926
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• 2003

This paper presents a novel low voltage reference circuit under the MOS threshold voltage(V$_{th}$) in standard CMOS process. It is based on the weighted difference of the gate-source voltages of an NMOS and a PMOS operating in saturation region. The voltage reference is designed for low power OLED driver ICs. The proposed circuit is designed using 0.35${\mu}{\textrm}{m}$ CMOS technology. The minimum supply voltage is 2V, and the typical temperature coefficient is 99.6ppm/ C.C.