• Korean Journal of Materials Research
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• v.13 no.1
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• pp.43-47
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• 2003

As and BF$_2$dopants are implanted for the formation of source/drain with dose of 1${\times}$10$^{15}$ ions/$\textrm{cm}^2$∼5${\times}$10$^{15}$ ions/$\textrm{cm}^2$ then formed cobalt disilicide with Co/Ti deposition and doubly rapid thermal annealing. Appropriate ion implantation and cobalt salicide process are employed to meet the sub-0.13 $\mu\textrm{m}$ CMOS devices. We investigated the process results of sheet resistance, dopant redistribution, and surface-interface microstructure with a four-point probe, a secondary ion mass spectroscope(SIMS), a scanning probe microscope (SPM), and a cross sectional transmission electron microscope(TEM), respectively. Sheet resistance increased to 8%∼12% as dose increased in $CoSi_2$$n^{＋}$ and $CoSi_2$$p^{V}$ , while sheet resistance uniformity showed very little variation. SIMS depth profiling revealed that the diffusion of As and B was enhanced as dose increased in $CoSi_2$$n^{＋}$ and $CoSi_2$$p^{＋}$ . The surface roughness of root mean square(RMS) values measured by a SPM decreased as dose increased in $CoSi_2$$n^{＋}$ , while little variation was observed in $CoSi_2$$p^{＋}$ . Cross sectional TEM images showed that the spikes of 30 nm∼50 nm-depth were formed at the interfaces of $CoSi_2$$n^{＋}$ / and $CoSi_2$/$p^{＋}$, which indicate the possible leakage current source. Our result implied that Co/Ti cobalt salicide was compatible with high dose sub-0.13$\mu\textrm{m}$ process.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.543-543
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• 2013

Thin-film transistors (TFTs) based on oxide semiconductors have been regarded as promising alternatives for conventional amorphous and polycrystalline silicon TFTs. Oxide TFTs have several advantages, such as low temperature processing, transparency and high field-effect mobility. Lots of oxide semiconductors for example ZnO, SnO2, In2O3, InZnO, ZnSnO, and InGaZnO etc. have been researched. Particularly, zinc-tin oxide (ZTO) is suitable for channel layer of oxide TFTs having a high mobility that Sn in ZTO can improve the carrier transport by overlapping orbital. However, some issues related to the ZTO TFT electrical performance still remain to be resolved, such as obtaining good electrical contact between source/drain (S/D) electrodes and active channel layer. In this study, the bottom-gate type ZTO TFTs with staggered structure were prepared. Thin films of ZTO (40 nm thick) were deposited by DC magnetron sputtering and performed at room temperature in an Ar atmosphere with an oxygen partial pressure of 10%. After annealing the thin films of ZTO at $400^{\circ}C$ or an hour, Cu, Mo, ITO and Ti electrodes were used for the S/D electrodes. Cu, Mo, ITO and Ti (200 nm thick) were also deposited by DC magnetron sputtering at room temperature. The channel layer and S/D electrodes were defined using a lift-off process which resulted in a fixed width W of 100 ${\mu}m$ and channel length L varied from 10 to 50 ${\mu}m$. The TFT source/drain series resistance, the intrinsic mobility (${\mu}i$), and intrinsic threshold voltage (Vi) were extracted by transmission line method (TLM) using a series of TFTs with different channel lengths. And the performances of ZTO TFTs were measured by using HP 4145B semiconductor analyzer. The results showed that the Cu S/D electrodes had a high intrinsic field effect mobility and a low effective contact resistance compared to other electrodes such as Mo, ITO and Ti.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.1-6
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• 2012

This paper presents the extraction and analysis of small-signal parameters of tunneling field-effect transistors (TFETs) by using TCAD device simulation. The channel lengths ($L_G$) of the simulated devices varies from 50 nm to 100 nm. The parameter extraction for TFETs have been performed by quasi-static small-signal model of conventional MOSFETs. The small-signal parameters of TFETs with different channel lengths were extracted according to gate bias voltage. The $L_G$-dependency of the effective gate resistance, transconductance, source-drain conductance, and gate capacitance are different with those of conventional MOSFET. The $f_T$ of TFETs is inverely proportional not to $L_G{^2}$ but to $L_G$.

• Korean Journal of Materials Research
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• v.13 no.6
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• pp.398-403
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• 2003

Shallow $p^{＋}$ n junction was formed using a ULE(ultra low energy) implanter. Deactivation phenomena were investigated for the shallow source/drain junction based on measurements of post-annealing time and temperature following the rapid thermal annealing(RTA) treatments. We found that deactivation kinetics has two regimes such that the amount of deactivation increases exponentially with annealing temperature up to $850^{\circ}C$ and that it decreases linearly with the annealing temperature beyond that temperature. We believe that the first regime is kinetically limited while the second one is thermodynamically limited. We also observed "transient enhanced deactivation", an anomalous increase in sheet resistance during the early stage of annealing at temperatures higher than X$/^{\circ}C$. Activation energy for transient enhanced deactivation was measured to be 1.75-1.87 eV range, while that for normal deactivation was found to be between 3.49-3.69 eV.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.67.1-67.1
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• 2012

Graphene has attracted much attention for future nanoelectronics due to its superior electrical properties. Owing to its extremely high carrier mobility and controllable carrier density, graphene is a promising material for practical applications, particularly as a channel layer of high-speed FET. Furthermore, the planar form of graphene is compatible with the conventional top-down CMOS fabrication processes and large-scale synthesis by chemical vapor deposition (CVD) process is also feasible. Despite these promising characteristics of graphene, much work must still be done in order to successfully develop graphene FET. One of the key issues is the process technique for gate dielectric formation because the channel mobility of graphene FET is drastically affected by the gate dielectric interface quality. Formation of high quality gate dielectric on graphene is still a challenging. Dirac voltage, the charge neutral point of the device, also strongly depends on gate dielectrics. Another performance killer in graphene FET is source/drain contact resistance, as the contact resistant between metal and graphene S/D is usually one order of magnitude higher than that between metal and silicon S/D. In this presentation, the key issues on graphene-based FET, including organic-inorganic hybrid gate dielectric formation, controlling of Dirac voltage, reduction of source/drain contact resistance, device structure optimization, graphene gate electrode for improvement of gate dielectric reliability, and CVD graphene transfer process issues are addressed.

• Korean Journal of Materials Research
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• v.24 no.3
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• pp.140-144
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• 2014

The contact mechanism of devices is usually researched at electrode contacts. However, the contact between a dielectric and channel at the MOS structure is more important. The graphene was used as a channel material, and the thin film transistor with MOS structure was prepared to observe the contact mechanism. The graphene was obtained on Cu foil by the thermal decomposition method with $H_2$ and $CH_4$ mixed gases at an ambient annealing temperature of $1000^{\circ}C$ during the deposition for 30 min, and was then transferred onto a $SiO_2/Si$ substrate. The graphene was doped in a nitrogen acidic solution. The chemical properties of graphene were investigated to research the effect of nitric atoms doping. The sheet resistance of graphene decreased after nitrogen acidic doping, and the sheet resistance decreased with an increase in the doping times because of the increment of negative charge carriers. The nitric-atom-doped graphene showed the Ohmic contact at the curve of the drain current and drain voltage, in spite of the Schottky contact of grapnene without doping.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.7
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• pp.1668-1672
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• 2009

In this study, the method by Robertson which has been most commonly used for classifying soils, using piezocone test results, was compared with that by Schneider which was most recently proposed. Both methods were applied to the soils in Gyeonggi province and the classifying results were investigated. It has been found that the difference between the results according to the methods was not so large and Schneider's method showed slightly better results for clay region and vice versa. Such factors as large field database, normalized tip resistance, pore water pressure, and drain condition were found to need further research for more reliable soil classification.

• Journal of Convergence for Information Technology
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• v.11 no.11
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• pp.159-165
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• 2021

A fin channel with a fin width of 20 nm and a gradually increased source/drain extension regions are fabricated on a bulk silicon wafer by using a three-dimensional selective oxidation. The detailed process steps to fabricate the proposed fin channel are explained. We are demonstrating their preliminary characteristics and properties compared with those of the conventional fin field effect transistor device (FinFET) and the bulk FinFET device via three-dimensional device simulation. Compared to control devices, the three-dimensional selective oxidation fin channel MOSFET shows a higher linear transconductance, larger drive current, and lower series resistance with nearly the same scaling-down characteristics.

• Journal of Semiconductor Engineering
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• v.3 no.2
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• pp.161-167
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• 2022

Electrical characteristics of LDMOS power device with LDD(Lightly Doped Drain) structure is studied with variation of the region of channel and LDD. The channel in LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of CMOS inverter. Two-dimensional TCAD MEDICI simulation is used to study hot-carrier effect, on-resistance Ron, breakdown voltage, and transient switching characteristic. The voltage-transfer characteristics and on-off switching properties are studied as a function of the channel length and doping levels. The digital logic levels of the output and input voltages are analyzed from the transfer curves and circuit operation. Study indicates that drain current significantly depends on the channel length rather than the LDD region, while the switching transient time is almost independent of the channel length. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.654-656
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• 2008

We enhanced the conductivity of PEDOT-PSS by mixing with glycerol and fabricated the low contact resistance of source and drain[S/D] electrodes of OTFT with PEDOT-PSS by ink-jetting printing. The contact resistance was much smaller by seven times than Au with $200k{\Omega}$ at $V_G=-5V$. For the bottom contacted OTFTs, the performance was comparable to OTFTs with Au electrodes with the field effect mobility of $0.2\;cm^2/V s$.