• 대한전기학회:학술대회논문집
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• 대한전기학회 2011년도 제42회 하계학술대회
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• pp.25-26
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• 2011

In this paper, we investigated the effect of various annealing processes on the electrical characteristics of oxide thin film transistors (TFTs). When we annealed the TFT devices before and after source/drain (S/D) process, we could observe the different electrical characteristics of oxide TFTs. When we annealed the TFTs after deposition of transparent indium zinc oxide S/D electrodes, the annealing process decreased the contact resistance but increased the resistivity of S/D electrodes. The field effect mobility, subthreshold slope and threshold voltage of the oxide TFTs annealed before and after S/D process were 5.83 and 4.47 $cm^2$/Vs, 1.20 and 0.82 V/dec, and 3.92 and 8.33 V respectively. To analyze the differences, we measured the contact resistances and the carrier concentrations using transfer length method (TLM) and Hall measurement.

• 대한전기학회논문지
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• 제43권2호
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• pp.251-258
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• 1994

To apply the Power MOSFET to the high powerd circuits, the parallel operation of the Power MOSFET must be considered because of their low power rating. This means, in practical applications, design methods for the parallel operations are required. However, it is very difficult to investigate the problem of parallel operations by directly changing the internal parameters of the MOSFET. Thus, in this paper, the effects of internal parameters for the parallel operation are investigated using SPICE program which is often used and known that the program is very reliable. The investigation results show that while the gate resistance and gate capacitances are the parameters which affect to the dynamic switching operations, the drain and source resistances are the parameters which affect to the steady-state current unbalances. Through this investigation, the design methods for the parallel operation of the MOSFET are suggested, which, in turn, contributes to the practical use of Power MOSFETs.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.13-16
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• 2002

In this study, the electrical characteristics of 100v-Class LDMOSFET for high temperature applicat -ions such as electronic control systems of automo -biles and motor driver were investigated. Measurement data are taken over wide range of temperature(300k-SOOK) and various gate length(1.5 #m-3.0#m, step 0.3). In high temperature condition(>500k), drain current decreased over 30%, and specific on- resistance increased about three times in comparison with room temperature. Moreover, the ratio ROJBV, a figure of merit of the device, increased with increasing temperature.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1077-1080
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• 2003

This paper show the measured result of electrical characteristics of SOI-LDMOSFET that is one of the high voltage devises. Especially, we observed changes of breakdown voltage, threshold voltage, on-resistance, drain current, and transconductance in accordance with drift length, main parameter of LDMOSFET. Also, we achieved reliability analysis about device operation in high temperature environment because LDMOS is applied to smart power IC.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.683-686
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• 2003

In this paper, we have investigated electrical characteristics of TRENCH GATE POWER MOSFET in the temperature range of 300K to 500K. The results of this study indicate that on-resistance and breakdown voltage increase with the temperature ,but drain current, threshold voltage and transconductance decrease with the temperature. Especially, it is observed that electrical characteristics are improved as numerical unit cells are increased.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.157-163
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• 2002

A new flash EEPROM device with p^＋ poly-Si control gate and n^＋ poly-Si floating side gate was fabricated and characterized. The n^＋ poly-Si gate is formed on both sides of the p^＋ poly-Si gate, and controls the underneath channel conductivity depending on the number of electron in it. The cell was programmed by hot-carrier-injection at the drain extension, and erased by direct tunneling. The proposed EEPROM cell can be scaled down to 50 nm or less. Shown were measured programming and erasing characteristics. The channel resistance with the write operation was increased by at least 3 times.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.201-204
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• 2001

LDMOSFET devices operated at low temperature have applications on satellite, space shuttle and low temperature system, etc. In this study, we measured the electrical characteristics of 100v Class LDMOSFET for low temperature application. Measurement data are taken over a wide range of temperatures (100K-300K) and various drift region lengths(6.6${\mu}{\textrm}{m}$, 8.4${\mu}{\textrm}{m}$, 12.6${\mu}{\textrm}{m}$). Maximum transconductance, $g_{m}$ and drain current at low temperatures(~100K) increased over about 260%, 50% respectively, in comparison with the data at room temperature. Breakdown voltage B $V_{ds}$, and specific on- resistance decreased. Besides, ratio $R_{on}$ BV, a figure of merit of the device, decreased with decreasing temperature.

• 한국콘크리트학회:학술대회논문집
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• 한국콘크리트학회 2000년도 봄 학술발표회 논문집
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• pp.333-338
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• 2000

At present, reinforced concrete pipe has been widely used as drain pipe. However, many reinforced concrete pipe is exposed at deteriorated environment by the growth of a sulfur-oxidizing bacterium isolated from corroded concrete. The purpose of this study is to evaluate the effects of lining by polymer-modified mortar on the development in durability of reinforced concrete pipe. Polymer-modified mortars ate prepared with various polymer typer as cement modifier and polymer-cement ratio and rested for compressive and flexural strengths, adhesion in tension, acid resistance test, freezing and thawing test, and lining test of product in the field. From the rest results, it is apparent that polymer-modified mortars have good mechanical properties and durability as lining material. In practice, all polymers can be used as lining materials for reinforced concrete pip, and type of polymer, and polymer-cement ratio and curing conditions are controlled for good lining product.

• 대한전자공학회논문지
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• 제26권9호
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• pp.1375-1380
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• 1989

Mobility reduction parameters are extracted using a method based on the exploitatiion of Id-Vg and Gm-Vg characteristics of short channel n-MOSFETs in strong inversion region at room temperature. It is found that the reduction of the maximum field effect mobility, \ulcornerFE,max, with the channel length is due to i) the difference between the threshold voltage and the gate voltage which corresponds to the maximum transconductance, and ii) the channel length dependence of the mobility attenuation coefficient, \ulcorner The low field mobility, \ulcorner, is found to be independent of the channel length down to 0.25 \ulcorner ofeffective channel length. Also, the channel length reduction, -I, the mobility attenuation coefficient, \ulcorner the threshold voltage, Vt, and the source-drain resistance, Rsd, are determined from the Id-Vg and -gm-Vg characteristics n-MOSFETs.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 C
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• pp.1630-1632
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• 1997

We have investigated activation phenomena of implanted ions on silicon wafers using microwave(2.45GHz). It is found that the higher concentration of impurities makes the better activation effects by microwave annealing. We have exposed poly-Si TFTs by microwave in order to anneal and improved the device performance. Microwave activates source/drain ions and lowers the contact resistance so that the current of the poly-Si TFTs increases. In addition, the leakage current of hydrogen passivated poly-Si TFTs is decreased after microwave annealing, due to the diffusion of hydrogen ions and curing the defects in the poly-Si active channel.