• Journal of the Korea Institute of Military Science and Technology
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• v.8 no.1 s.20
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• pp.39-48
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• 2005

After the development of the Firefly, flight tests have been performed to verify the performance and get the parameters for the mathematical model of the aircraft. The flight test data is used to get parameters for the mathematical model of the aircraft through the parameter identification process. An arbitrary control input is applied to the test flight which is a part of parameter identification process. A square wave has been used a control input which is called Doublet signal. The aspect of the signal is same length and magnitude in both (+) and (-) directions such as sine wave. The Doublet signal is composed of a dominant frequency and many high frequencies, so that it is appropriate signal to excite the motion of an aircraft. In this paper, the control input of the flight test data has been analyzed to check the efficiency of the control input using DFT(Discrete Fourier Transform). From the result of analysis, an alternative input was extracted.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.9B
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• pp.1570-1578
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• 2000

A quadrature pair of filter banks that are composed of a pair of cosine and sine modulated filter banks is applied to MC-CDMA data transmultiplexing in the view point of mitigating inter-channel interferences. Exploiting superior capabilities of wavelet properties in composing the filter banks the proposed scheme is capable of compromising inter-channel interference problems better than the conventional DFT-based MC-CDMA due to superior subchannelization effects. To verify the behavior of our proposed MC-CDMA system based on the quadrature filter banks the reverse-link bit error rates with respect to signal-to-noise ratio under Rayleigth fading and additive white Gaussian noise channel environments are computed. The results show an improved system performance over the conventional MC-CDMA in the view point of minimizing interference effects.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.37-42
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• 2000

In this paper, The high-speed, low-Power analog-to-digital conversion structure is proposed using the pipelined comparator away for high-speed conversion rate and the successive- approximation structure for low-power consumption. This structure is the successive-approximation structure using pipelined comparator array to change the reference voltage during the holding time. An 8-bit 10MS/s analog-to-digital converter is designed using 0.8${\mu}{\textrm}{m}$ CMOS technology. The INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 41㏈ at a sampling rate of 10MHz with 100KHz sine input signal. The Power consumption is 4.14㎽ at 10MS/s.