• Corrosion Science and Technology
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• v.8 no.3
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• pp.93-102
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• 2009

The direct-current electroetching of high purity aluminum in hot aqueous-chloride solution produces a high density of micrometer-wide tunnels whose walls are made up of the {100} planes and penetrate aluminum in the <100> directions at rates of micrometer per second. In the process of the alternating-current pitting of aluminum, cathodic polarization plays an important role in the nucleation and growth of the pits during the subsequent polarization. The direct-current tunnel etching and alternating-current etching of aluminum are basically related to the formation of poorly crystallized or amorphous passive films. If the passive film forms on the wall, a natural misfit exists between the film and the aluminum substrate, which in turn gives rise to stress in both the film and the substrate. Even though the amorphous films do not have directed properties, their stresses are influenced by the substrate orientation. The films on elastically soft substrate are likely to be less stressed and more stable than those on elastically hard substrate. The hardest and softest planes of aluminum are the {111} and {100} planes, respectively. Therefore, the films on the {111} substrates are most likely to be attacked, and those on the {100} substrates are least likely to be attacked. For the tunnel etching, it follows that the tunnel walls tend to consist of the {100} planes. Meanwhile, the tunnel tip, where active corrosion takes place, tend to be made of four closely packed {111} planes in order to minimize the surface energy, which gives rise to the <100> tunnel etching.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.