• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10A
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• pp.969-979
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• 2002

This paper proposes an novel method of minimizing Interference which causes data decision error in digital wireless communications. In this method, in order to suppress ISI which is caused by the phase difference between the transmitted and received signal phases, the transmitted and received signals are always kept orthogonal by compensating the transmitted signal for detecting the phase noise and the delay of the received signal was implemented by MOS circuits. To delay the phase of the signal, additive white Gaussian noise (AWGN) environment was used. The phase and delay of the signal transmitted through AWGN channel were compensated in the modulator of the transmitter and the compensated signal was demodulated using quasi-direct conversion receiver and QPSK demodulator. ISI suppression was achieved by keeping the orthogonality between the compensated transmitted signal and the receive signal. The error probability of data decision was compared. By simulation the proposed system was proved to be effective in minimizing the ISI.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.3
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• pp.153-159
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• 1989

This paper describes the algorithms employed in the preprocessing stage of the timing simulator, TSIM1.0, which is based on the Waveform Relaxation Method (WRM) at the CELL-level. The preprocessing stage in TSIM1.0 (1)partitions a given circuit into DC connected blocks (DCB's) (2) forms strongly connected circuts (SCC's) and (3) orders CELL's Also, the efficient waveform management technique for the WRM is described, which allows the overwriting of the waveform management technique for the WRM is described. which allows the overwriting of the waveform information to save the storage requirements. With TSIM1.0, circuits containing up to 5000 MOSFET's can be analyzed within 1 hour computation time on the IBM PC/AT. The simulation results for several types of MOS digital circuits are given to verify the performance of TSIM1.0.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.10
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• pp.30-37
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• 1998

An analog array with a 1.2 $\mu\textrm{m}$ double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.161-166
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• 1999

The global trends of mobile communication system is moving toward digitizing, high-speed and large-capacity. Also, to utilize the limited frequency-resource efficiently, spread spectrum system is a mainstream. In this study we are concerning with the fast frequency-hopping system. Instead of the PLL with many problems such as phase-noise, we used the DDS is popular in these days minimizes the disadvantage of PLL. In the case the FFH system is designed using the PLL, it is difficult to be satisfied of the design conditions such as RF badwidth and the settling time of PLL, and it has limitation because of complex circuit by using the balanced modulator. In this study, we evaluated the performance in order to design the FFH system using the DDS. The system that has the improvement of error rate, 1Mhps hopping rate and 5MHz RF bandwidth is designed and evaluated.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.2
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• pp.829-834
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• 2011

Exposure process is the most important technology to fabricate highly integrated circuit. Up to now, mask type lithography process has been generally used. However, it is not efficient for small quantity and/or frequently changing products. Therefore, maskless lithography technology is raised in exposure process. In this study, relations between multi-beam energy and overlay were analyzed. Exposure experiment of generating pattern was performed. It was from presented scan line by multi- beam simulation. As a result, optimal scan line distance was proposed by simulation, and micro pattern accuracy could be improved by exposure experiment using laser direct imaging system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.4
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• pp.712-720
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• 1994

In digital mobile communication systems, the convolutional coding is considered as the optimum error correcting scheme. Recently, the Viterbi algorithm is widely used for the decoding of convolutional code. Most Viterbi decoder has been proposed in conde rate R=1/2 or 2/3 with memory components (m) less than 3. which degrades the error correcting capability because of small code constraints (K). We consider the design method for typical code rate R=1/2, K=7(171,133) convolutional code with memory components, m=6. In this paper, a novel construction method is presented which combines maximum likelihood decoding with a state transition double detection and comparison method. And the designed circuit has the error-correcting capability of random 2 bit error. As the results of logic simulation, it is shown that the proposed Viterbi decoder exactly corrects 1 bit and 2 bit error signal.

• Journal of Sensor Science and Technology
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• v.20 no.4
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• pp.272-278
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• 2011

Recently, the performance of binaural hearing aids is rapidly improved with the technology advancement of wireless communication, digital signal processing, and integrated circuit design. However, the previous hearing aids developer platforms can't be applied to binaural hearing aids developing, because it has no consideration for wireless communication and binaural hearing control. Also, the previous developer platforms are not easy to use for the algorithm development, because programming languages are limited. In this paper, we designed and implemented the open platform board for binaural hearing aids developing. The designed board can be programmed by general programming language and can be used wireless communication module. In order to verify the designed open platform board, we used the volume control algorithm using two open platform board. As a result of experiment, we verified the performance of designed and implemented open platform board that was successfully operated the binaural hearing control and the wireless communication.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.8
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• pp.1805-1810
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• 2014

The phase noise spectrum distribution for remote controller using the BPSK mode and low data rate of 50 kbps was designed and proposed in this paper. In case of applying the BPSK that transmission performance is superior to FSK method, the performance degradations due to phase noise are generated. To minimize the phase noise effect, it is important to dispatch the digital signal in channel environment with required phase noise characteristics. To provide the terminal design technique and the proper channel environment with required phase noise characteristics, the phase noise spectrum distribution was designed for required phase noise characteristics. By analyzing the phase noise effects for damping factor and noise bandwidth of the carrier recovery circuit, the phase noise spectrum design that consider the damping factor and noise bandwidth was performed. Based on the IESS-308 standards, also, the phase noise effects was analyzed. The phase noise spectrum design techniques and phase noise spectrum that is suitable to remote controller were proposed.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.10
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• pp.1275-1283
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• 1999

본 논문은 CMOS 디지털 회로에서의 전력 소모의 주원인인 신호의 천이중에서 회로의 동작에 직접적인 영향을 미치지 않는 불필요한 신호의 천이인 글리치를 줄이기 위한 효율적인 알고리즘을 제시한다. 제안된 알고리즘은 회로의 지연 증가 없이 게이트 사이징과 버퍼 삽입에 의해 경로 균등(path balancing)을 이룸으로써 글리치를 감소시킨다. 경로 균등화를 위하여 먼저 게이트 사이징을 통해 글리치의 감소와 동시에, 게이트 크기의 최적화를 통해 회로 전체의 캐패시턴스까지 줄일 수 있으며, 게이트 사이징 만으로 경로 균등화가 이루어지지 않을 경우 버퍼 삽입으로 경로 균등화를 이루게 된다. 버퍼 자체에 의한 전력 소모 증가보다 글리치 감소에 의한 전력 감소가 큰 버퍼를 선택하여 삽입한다. 이때 버퍼 삽입에 의한 전력 감소는 다른 버퍼의 삽입 상태에 따라 크게 달라질 수 있어 ILP (Integer Linear Program)를 이용하여 적은 버퍼 삽입으로 전력 감소를 최대화 할 수 있는 저전력 설계 시스템을 구현하였다. 제안된 알고리즘은 LGSynth91 벤치마크 회로에 대한 테스트 결과 회로의 지연 증가 없이 평균적으로 30.4%의 전력 감소를 얻을 수 있었다.Abstract This paper presents an efficient algorithm for reducing glitches caused by spurious transitions in CMOS logic circuits. The proposed algorithm reduces glitches by achieving path balancing through gate sizing and buffer insertion. The gate sizing technique reduces not only glitches but also effective capacitance in the circuit. In the proposed algorithm, the buffers are inserted between the gates where power reduction achieved by glitch reduction is larger than the additional power consumed by the inserted buffers. To determine the location of buffer insertion, ILP (Integer Linear Program) has been employed in the proposed system. The proposed algorithm has been tested on LGSynth91 benchmark circuits. Experimental results show an average of 30.4% power reduction.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.502-502
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• 2007

Current thin film process using memory device fabrication process use expensive processes such as manufacturing of photo mask, coating of photo resist, exposure, development, and etching. However, direct printing technology has the merits about simple and cost effective processes because inks are directly injective without mask. And also, this technology has the advantage about fabrication of fine pattern line on various substrates such as PCB, FCPB, glass, polymer and so on. In this work, we have fabricated the fine and thick metal pattern line for the electronic circuit board using metal ink contains Ag nano-particles. Metal lines are fabricated by two types of printing methods. One is a conventional printing method which is able to quick fabrication of fine pattern line, but has various difficulties about thick and high resolution DPI(Dot per Inch) pattern lines because of bulge and piling up phenomenon. Another(Second) methods is sequential printing method which has a various merits of fabrication for fine, thick and high resolution pattern lines without bulge. In this work, conductivities of metal pattern line are investigated with respect to printing methods and pattern thickness. As a result, conductivity of thick pattern is about several un.