• Journal of the Korea Society of Computer and Information
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• v.17 no.2
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• pp.113-118
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• 2012

In this paper, we discuss the design of the Digital Down Converters for the IEEE 802.11 wireless LAN receiver, which can be used for the customized receiver. The customized receiver can be used for special puropsed services which cannot be realized using the general custom chip. In the OFDM receiver, DDC receives the up sampled Inphase/Quadrature signal from the AD converter and process down sampling and filtering procedures using the Cascaded Intergrator Filter and FIR filters. We discuss the structure and design methodology of DDC's and analyze the simulation results.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.5
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• pp.327-329
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• 2005

Conventional CDDA(Compact Disc Digital Audio) system has limitation which means that bandwidth and resolution of the sign릴 are determined by the sampling frequency and quantization bit, 44.1kHz and 16 bit respectively. Though, new medium such as DVD-audio is developed for high-resolution audio recording, it has high complexity and difficulty in manufacturing process. So, CDDA is a widely used medium for high fidelity audio yet. In this paper, we design a new encoding system for high-resolution audio signal which has backward compatible with conventional CDDA. By evaluating for the encoding and decoding process. we verify the availability of our proposed system.

• Journal of the Korea Society of Computer and Information
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• v.4 no.3
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• pp.47-52
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• 1999

The efficiency of an adder which plays an important role in micro-process and DSP greatly depends on the kinds of carry generation method. So in this paper. I used both CLA excellent in the speed and CSA best in the chip-size. The 64bit adder is designed with high speed which is two optimum combination. Therefore this paper suggested the way of CLSA improving both speed and chip-size. and proved the excellence of the designed circuit.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.1
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• pp.56-63
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• 2009

Nowdays, Most of Internet Contents delivered as a compressed file. It gives many advantages like deduction of communication bandwidth and transmission time etc. In case of JPEG Compression, Quantization is the most important procedure which accomplish the compression. In general signal processing, Quantization is the process which converts continuous analog signal to discrete digital signal. As you known already, Quantization over JPEG compression is to reduce magnitude of pixel value in spatial domain or coefficient in frequency domain. A lot of Data Hiding algorithms also developed to applicable for those compressed files. In this paper, we are going to unveil the influence of quantization table which used in the process of JPEG compression. Even thought most of algorithm modify frequency coefficients with considering image quality, they are ignoring the influence of quantization factor corresponding with the modified frequency coefficient. If existing algorithm adapt this result, they can easily evaluate their performances.

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.329-334
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• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.16 no.5
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• pp.69-77
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• 2017

This paper introduces an optical encoder using the reflection in the slit. The digital optical encoder is a sensor to generate a pulse according to the displacement. An optical encoder is composed of 3 parts: light source, slit plate and light-receiving element. In a conventional encoder, one slit produces one signal. The resolution of the digital optical encoder is determined by the number of slits in the encoder plate. The small slit size is most important among the factors that determine the resolution in a generic-type optical encoder. However, a small slit has low productivity and technical difficulties, so analog optical encoders have emerged as an alternative. Nonetheless, this alternative requires additional circuitry and equipment because of the noise and drafts in the analog signals. A new sensor is presented in this paper with a high resolution and a slit of the same size using the reflection in the slit. Then, the path of the light that passes through the slit ccording to the shape was analyzed, and some paths were expressed in the mathematical expressions. In addition, the optical paths were analyzed in the rectangular, octagonal, and circular encoders, and shown the obtained number of signals per slit by using them. Thus, we confirm that this method has the best performance in circle-shaped slits.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.109-112
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• 2007

Definition-Enhancement of the digitalized image has been being made researches continuously due to application a camera to a mobile-apparatus and the advent of a digital camera. In particular, the inputted image from a sensor goes through the process of ISP(Image Signal Process) prior to output as a visual image. The high-frequency components are offset by LPF(Low Pass Filter) that eliminates the noise of high spatial-frequency at the moment. In this paper, we propose an algorithm that outputs more vivid image by using adaptive-HPF(High Pass Filter) that has apt coefficients for diverse conditions of an image edge, nevertheless we do not employ any Edge-Detection algorithm to enhance a blurred image.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1543-1551
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC(Digital-to-Analog Converter) is employed to overcome the problems of dithering scheme. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The proposed DCO has been designed in a $0.13{\mu}m$ CMOS process. Measurement results shows that the designed DCO oscillates in 2.8GHz~3.5GHz and has a frequency tuning range of 660MHz and a resolution of 73Hz at 2.8GHz band. The designed DCO exhibits a phase noise of -119dBc/Hz at lMHz frequency offset. The DCO core consumes 4.2mA from l.2V supply. The chip area is $1.3mm{\times}1.3mm$ including pads.

• The Journal of the Korea Contents Association
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• v.10 no.12
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• pp.10-17
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• 2010

In this paper, we design digital D-PHY link chip controling DSI (Display Serial Interface) that meets MIPI (Mobile Industry Processor Interface) standard. The D-PHY supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions. For low power consumption, the unit blocks in digital D-PHY are optionally switched using the clock gating technique. The proposed low power digital D-PHY is simulated and compared with conven tional one about power consumption on each transaction mode. As a result, power consumptions of TX, RX, and total in HS mode decrease 74%, 31%, and 50%, respectively. In LP mode, power reduction rates of TX, RX, and total are 79%, 40%, and 51.5%, separately. We implemented the low power MIPI D-PHY digital chip using $0.13-{\mu}m$ CMOS process under 1.2V supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.693-697
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• 2007

The SSB modem performs the modulation process which converts the digital voltage level to the audible frequency band signal and the demodulation process which converts reversely the audible frequency signal to the digital voltage level. The modulator and the demodulator are implemented with a single DSP chip. Because of the SSB specific character, the distortion occurs when the frequency is changed. This distortion has no effect on voice communication, but it has an significant effect on data communication. In other words, it is impossible to send data stream with adjacent 2 periods. Therefore, in case of using 2-tone FSK, it is needed to send at least 3 periods to transmit 1 bit. Therefore we implemented the modem using modified phase-delay shift keying to transmit 1 tone signal for high speed transmission. In the 1200[bps] mode, it generates 0, $187{\mu}s$ delay time at 1.3kHz symbol frequency, and in the 2400[bps] mode, 0, $70{\mu}s$, $130{\mu}s$, $200{\mu}s$ delay time at 1.5kHz symbol frequency. Finally, in the maximum 3600[bps] mode, it generates 0, $100{\mu}s$, $160{\mu}s$, $250{\mu}s$ delay time at 2.0kHz symbol frequency. The measured results of the implemented SSB modem shows a good transfer functional characteristic by spectrum analyzer, almost same bandwidth in pass band and 20dB higher SNR comparing the German PACTOR and American CLOVER and in the experimental transmitting test, we verified the transmitted data is received correctly in platform.