• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.7
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• pp.86-98
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• 1996

Modulation and demodualtion circuits of chaos frequency shift keying have been implemented using chua's circuits. The modulatin circuit, which is designed ot perform the frequency-doubling by coupled synchronization wihtout changing the intrinsic characteristics of its two chaos signals generated, modulates the digital input signals. The demodulation circuit detects the digital input signals form carrier by drive synchronization. these circuits, which are simplest until now and have no restriction to their digital input amplitudes, perform the aimed functions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.5
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• pp.323-328
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• 2001

A new time-to-digital converter is proposed which is based on a capacitor and a counter. The conventional time-to-digital converter requires rather longer processing time than the input time interval to obtain an accurate digital output. The resolution of the converted digital output is constant independent on the input time interval. However this study proposes the circuit in which the converted digital output can be obtained without delay time, and both the input time interval and the resolution can be easily improved through controlling passive device parameters.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.16 no.2
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• pp.291-297
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• 1998

In order to accomplish the digital map production I/O devices should be used which are used for data input procedure to convert original paper map(hardcopy) data into computer compatible digital map data, and for the mapsheet output procedure of worked out data. For the input device, digitizer and scanner are most frequently used. Digitizer has possibility of direct production of digital data, and are mainly used for input procedure of partly plotted source map. In contrary, scanner is rather easy to operate the instrument, so that is widely used for the input procedure of original sheet map. In this study, to extract the input device characteristics, some kinds of digitizers and scanners were cheesed and used for the positional error analysis through the operational method and types of instruments. Also for the output device characteristics, some kinds of plotter and materials are used and compared to analyze the positional error through the instrumental types and output sheet materials.

• Proceedings of the KIEE Conference
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• 2001.04a
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• pp.240-243
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• 2001

This paper presents the digital controller using variable gain for single-phase power factor correction (PFC) converter. Generally, the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This is why input current is distorted under low input voltage. In particular, a digital controller has more time delay than an analog controller which degrades characteristics of control loop. So, it causes the problem that the gain of current control loop isn't increased enough. In addition, the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult. In this paper, the improved digital control method for single-phase power factor converter is presented. The variable gain according to input voltage and input current help to improve current shape. The 800W converter is manufactured to verify the proposed control method.

• Journal of Korea Society of Digital Industry and Information Management
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• v.12 no.4
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• pp.71-79
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• 2016

This study proposes a performance model of a shared bus multi-processor system and analyzes the effect of input/output types on system performance and overload of shared resources. This system performance model reflects the memory reference time in relation to the effect of input/output types on shared resources and the input/output processing time in relation to the input/output processor, disk buffer, and device standby places. In addition, it demonstrates the contribution of input/output types to system performance for comprehensive analysis of system performance. As the concept of workload in the probability theory and the presented model are utilized, the result of operating and analyzing the model in various conditions of processor capability, cache miss ratio, page fault ratio, disk buffer hit ratio (input/output processor and controller), memory access time, and input/output block size. A simulation is conducted to verify the analysis result.

• Journal of Power Electronics
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• v.6 no.1
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• pp.83-93
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• 2006

A new high efficiency and low profile on-board DC/DC converter for digital car audio amplifiers is proposed. The proposed converter shows low conduction loss due to the low voltage stress of the secondary diodes, a lack of DC magnetizing current for the transformer, and a lack of stored energy in the transformer. Moreover, since the primary MOSFETs are turned-on under zero-voltage-switching (ZVS) conditions and the secondary diodes are turned-off under zero-current-switching (ZCS) conditions, the proposed converter has minimized switching losses. In addition, the input filter can be minimized due to a continuous input current, and an output inductor is absent in the proposed converter. Therefore, the proposed converter has the desired features, high efficiency and low profile, for a viable power supply for digital car audio amplifiers. A 60W industrial sample of the proposed converter has been implemented for digital car audio amplifiers with a measured efficiency of $88.3\%$ at nominal input voltage.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.1
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• pp.183-190
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• 2012

Mobile web applications are different from desktop web applications because of their small screen size and small user input devices. Therefore user interface designers have spent their effort and time to re-design the user interface of mobile web applications to meet these differences. In this paper, we introduce five user interface patterns for mobile web applications to reduce their effort and time. Two of them are for utilizing small screen size efficiently, and they are space overloading pattern and data filtering pattern. These patterns enable designers to reduce screen usage. The other three patterns - data suggestion pattern, input reuse pattern, and incremental data input pattern - are for helping users' data input on mobile devices. These three patterns enable users to reduce direct data input. Our work will help user interface designers develop mobile web interface to utilize screen space efficiently and get data with less errors and less efforts from users.

• Smart Structures and Systems
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• v.22 no.2
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• pp.167-174
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• 2018

Digital input and output modules are widely used to connect digital sensors and actuators to automation systems. Digital I/O modules provide flexible connectivity extension to numerous sensors and actuators and protect systems from high voltages and currents by isolation. Components in digital I/O modules are inevitably affected by operating and environmental conditions, such as high voltage, high current, high temperature, and temperature cycling. Because digital I/O modules transfer signals or isolate the systems from unexpected voltage and current transients, their failures may result in signal transmission failures and damages to sensitive circuitry leading to system malfunction and system shutdown. In this study, the lifetime of optocouplers, one of the critical components in digital I/O modules, was predicted using Bayesian tracking approaches. Accelerated degradation tests were conducted for collecting the critical performance parameter of optocouplers, current transfer ratio (CTR), during their lifetime. Bayesian tracking approaches, including extended Kalman filter and particle filter, were applied to predict the failure. The performance of each prognostic algorithm was then compared using accuracy and robustness-based performance metrics.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.4
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• pp.243-250
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• 2005

Test methodology is diversity by devices and the number of test pattern is tremendous because the digital circuit includes TTL and CMOS family ICs as well as high density devices such as ROM and RAM. Accordingly, the quick and effective test strategy is required to enhance the test productivity. This paper proposes the test strategy which is able to be applied efficiently to the diversity devices on the digital circuit board by analyzing the structure and characteristic of the digital device. Especially, this test strategy detects the faulted digital device or the faulted digital circuit on the digital board using SSA(Serial Signature Analysis) technique based on the polynomial division theory The SSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Register) representing the characteristic equation. Also, the method to obtain the optimal signature analysis circuit is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• Proceedings of the IEEK Conference
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• summer
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• pp.199-203
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• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.