• Title/Summary/Keyword: digital encoding

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Fast Motion Estimation Algorithm for Efficient MPEG-2 Video Transcoding with Scan Format Conversion (스캔 포맷 변환이 있는 효율적인 MPEG-2 동영상 트랜스코딩을 위한 고속 움직임 추정 기법)

  • 송병철;천강욱
    • Journal of Broadcast Engineering
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    • v.8 no.3
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    • pp.288-296
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    • 2003
  • ATSC (Advanced Television System Committee) has specified 18 video formats for DTV (Digital Television), e.g., scan format, size format, and frame rate format conversion. Effective MPEG-2 video transcoders should support any conversion between the above-mentioned formats. Scan format conversion Is hard to Implement because it may often induce frame rate and size format conversion together. Especially. because of picture type conversion caused by scan format conversion, the computational burden of motion estimation (ME) in transcoding becomes serious. This paper proposes a fast ME algorithm for MPEG-2 video transcoding supporting scan format conversion. Firstly, we extract and compose a set of candidate motion vectors (MVs) from the input bit-stream to comply with the re-encoding format. Secondly, the best MV is chosen among several candidate MVs by using a weighted median selector. Simulation results show that the proposed ME algorithm provides outstanding PSNR performance close to full search ME, while reducing the transcoding complexity significantly.

Analysis of Intra Prediction for Digital Watermarking based on HEVC (HEVC기반의 디지털 워터마킹을 위한 인트라 예측의 분석)

  • Seo, Young-Ho;Kim, Bora;Kim, Dong-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.5
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    • pp.1189-1198
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    • 2015
  • Recently, with rapid development of digital broadcasting technology, high-definition video service increased interest and demand. supplied mobile and image device support that improve 4~16 time existing Full HD. Such as high-definition contents supply, proposed compression for high-efficiency video codec (HEVC). Therefore, watermarking technology is necessary applying HEVC for protecting ownership and intellectual property. In this paper, analysis of prediction mode in intra frame and study feasibility of watermarking in re-encoding based HEVC. Proposed detect un-changed blocks in intra frame, using the result of analysis prediction mode.

CPU Parallel Processing and GPU-accelerated Processing of UHD Video Sequence using HEVC (HEVC를 이용한 UHD 영상의 CPU 병렬처리 및 GPU가속처리)

  • Hong, Sung-Wook;Lee, Yung-Lyul
    • Journal of Broadcast Engineering
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    • v.18 no.6
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    • pp.816-822
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    • 2013
  • The latest video coding standard HEVC was developed by the joint work of JCT-VC(Joint Collaborative Team on Video Coding) from ITU-T VCEG and ISO/IEC MPEG. The HEVC standard reduces the BD-Bitrate of about 50% compared with the H.264/AVC standard. However, using the various methods for obtaining the coding gains has increased complexity problems. The proposed method reduces the complexity of HEVC by using both CPU parallel processing and GPU-accelerated processing. The experiment result for UHD($3840{\times}2144$) video sequences achieves 15fps encoding/decoding performance by applying the proposed method. Sooner or later, we expect that the H/W speedup of data transfer rates between CPU and GPU will result in reducing the encoding/decoding times much more.

A Steganography Method Improving Image Quality and Minimizing Image Degradation (영상의 화질 개선과 열화측정 시간을 최소화하는 스테가노그라피 방법)

  • Choi, YongSoo;Kim, JangHwan
    • Journal of Digital Contents Society
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    • v.17 no.5
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    • pp.433-439
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    • 2016
  • In this paper, we propose a optimized steganography how to improve the image degradation of the existing data hiding techniques. This method operates in the compressed domain(JPEG) of an image. Most of the current information concealment methods generally change the coefficients to hide information. And several methods have tried to improve the performance of a typical steganography method such as F5 including a matrix encoding. Those papers achieved the object of reducing the distortion which is generated as hiding data in coefficients of compressed domain. In the proposed paper we analyzed the effect of the quantization table for hiding the data in the compressed domain. As a result, it found that can decrease the distortion that occur in the application of steganography techniques. This paper provides a little (Maximum: approximately 6.5%) further improved results in terms of image quality in a data hiding on compressed domain. Developed algorithm help improve the data hiding performance of compressed image other than the JPEG.

Analysis and Experiment of Portrayal Process based on S-100 Standard of Marine Safety Information (해양안전정보의 S-100 표준 기반 표출 프로세스 분석 및 실험)

  • Kim, Hyoseung;Mun, Changho;Lee, Seojeong
    • Journal of Digital Contents Society
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    • v.19 no.7
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    • pp.1289-1296
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    • 2018
  • The e-Navigation promoted by the International Maritime Organization is a technology that provides marine-related information necessary for ship and shore side by electronic means for marine safety, security and protecting marine environment. The IHO S-100 standard is a geospatial standard that can express various hydrographic information. Various specifications including S-101 for electronic charts are being developed. In this paper, to help developers who are interested in implementing the technology of S-100, we not only analyze the process to portray the S-100 based data but also implement a case study on S-129 under keel clearance management. The portrayal process consists of data encoding and portrayal engine. Data encoding includes generation of application schema and data set. Portrayal engine is performed by the reform of the generated data set, the XSLT processing, and then the generation of drawing instructions.

A New Flash A/D Converter Adopting Double Base Number System (2개의 밑수를 이용한 Flash A/D 변환기)

  • Kim, Jong-Soo;Kim, Man-Ho;Jang, Eun-Hwa
    • Journal of the Institute of Convergence Signal Processing
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    • v.9 no.1
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    • pp.54-61
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    • 2008
  • This paper presents a new TIQ based CMOS flash 6-bit ADC to process digital signal in real time. In order to improve the conversion speed of ADC by designing new logic or layout of ADC circuits, a new design method is proposed in encoding logic circuits. The proposed encoding circuits convert analog input into digitally encoded double base number system(DBNS), which uses two bases unlike the normal binary representation scheme. The DBNS adopts binary and ternary radix to enhance digital arithmetic processing capability. In the DBNS, the addition and multiplication can be processed with just shift operations only. Finding near canonical representation is the most important work in general DBNS. But the main disadvantage of DBNS representation in ADC is the fan-in problem. Thus, an equal distribution algorithm is developed to solve the fan-in problem after assignment the prime numbers first. The conversion speed of simulation result was 1.6 GSPS, at 1.8V power with the Magna $0.18{\mu}m$ CMOS process, and the maximum power consumption was 38.71mW.

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A Study on Simple chip Design that Convert Improved YUV signal to RGB signal (개선된 YUV신호를 RGB신호로 변환하는 단일칩 설계에 관한 연구)

  • Lee, Chi-Woo;Park, Sang-Bong;Jin, Hyun-Jun;Park, Nho-Kyung
    • Journal of IKEEE
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    • v.7 no.2 s.13
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    • pp.197-209
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    • 2003
  • A current TV out format is quite different from that of HDTV or PC monitor in encoding techniques. In other words, a conventional analog TV uses interlaced display while HDTV or PC monitor uses Non-interlaced / Progressive-scanned display. In order to encode image signals coming from devices that takes interlaced display format for progressive scanned display, a hardware logic in which scanning and interpolation algorithms are implemented is necessary. The ELA(Edge-Based Line Average) algorithm have been widely used because it provided good characteristics. In this study, the ADI(Adaptive De-interlacing Interpolation) algorithm using to improve the ELA algorithm which shows low quality in vertical edge detections and low efficiency of horizontal edge lines. With the De-interlacing ASIC chip that converts the interlaced Digital YUV to De-interlaced Digital RGB is designed. The VHDL is used for chip design.

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An Implementation of the Canonical XML Algorithm (XML 정규화 알고리즘 구현)

  • 박기식;조인준;정회경
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.8
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    • pp.1698-1707
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    • 2003
  • These days, XML is accepted and used to e commerce market broadly. But by reason of XML document can exist same form logically but several other forms physically, several problems can happen in application that judge effectiveness as physical form such as XML digital signature. Therefore, it is recommending to propose and use canonical XML algorithm to change identical XML document physically equally logically in W3C to solve this problems. We implemented system that nm Canonical XML algorithm that suggested in W3C that can change to mon elaborate regular document. Thus, interoperable with other application that takes W3C recommendation Also, as well as use in digital signature system for web service is useful, use in several system that physical identify is required when it exchanges na document for web service interoperability are considered to be valuable. Moreover, Adding the transformation ability between universal encoding scheme and EUC­KR that is internal encoding scheme should be Canonical XML Algorithm that is suited to internal circumstances, and this should be a foundation technique of international interoperability confirmedness.

A High-Performance ECC Processor Supporting NIST P-521 Elliptic Curve (NIST P-521 타원곡선을 지원하는 고성능 ECC 프로세서)

  • Yang, Hyeon-Jun;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.4
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    • pp.548-555
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    • 2022
  • This paper describes the hardware implementation of elliptic curve cryptography (ECC) used as a core operation in elliptic curve digital signature algorithm (ECDSA). The ECC processor supports eight operation modes (four point operations, four modular operations) on the NIST P-521 curve. In order to minimize computation complexity required for point scalar multiplication (PSM), the radix-4 Booth encoding scheme and modified Jacobian coordinate system were adopted, which was based on the complexity analysis for five PSM algorithms and four different coordinate systems. Modular multiplication was implemented using a modified 3-Way Toom-Cook multiplication and a modified fast reduction algorithm. The ECC processor was implemented on xczu7ev FPGA device to verify hardware operation. Hardware resources of 101,921 LUTs, 18,357 flip-flops and 101 DSP blocks were used, and it was evaluated that about 370 PSM operations per second were achieved at a maximum operation clock frequency of 45 MHz.

Coast Evaluation Techniques for Mode Selection in Video Coding (동영상에서 모드 선택을 위한 코스트 평가 방법)

  • Song, Dae-Geon
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.13 no.6
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    • pp.275-280
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    • 2013
  • Recently, access networking BroadBand the high performance of the video equipment to the Internet via voice, video, multimedia services, such as dealing with the media information dissemination is becoming increasingly attracting attention. More video devices and network environments in the future to keep pace with the high-quality video using the form dealing with an increasingly diversified and shall utilization is expected. Among them, video encoding technology, image compression encoding technology of information technology is one of the central role. Video coding technology that requires a vast amount of information contained in the video signal and the appropriate amount of information to eliminate redundancy as the efficiency of the digital code representing video signal is developed as a technology is going. Therefore, this study applied to video coding mode selection in the cost evaluation methods to examine and to maximize the coding efficiency and the proposed method compared to the conventional method was confirmed excellence.