• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.5-8
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• 2001

In this paper, we have space vector PWM(Pulse Width Modulation) circuits on the FPGA(Field Programmable Gate Arry) chip designed by VHDL(Very high speed integrated circuit Hardware Description Language). This circuit parts was required at controlling the AC servo motor system and should have been designed with many discrete digital logics. In the result of this study, peripheral circuits are to be simple and the designed logic terms are robust and precise. Because of it's easy verification and implementation, we could deduced that the customize FPGA chip show better performance than that of circuit modules parts constituted of discrete IC.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.231-234
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• 1989

In recent, due to the advanced development of the power semiconductor devices, the Digital Simulation becomes essential in order to investigate the behavior of the system before the manufacturing of the system by using computer for design and analysis of Power Electronic systems. This paper develope the program so-called PECA, which can be applied for the Power Electronic circuits composing of power transistors, thyristers, GTOs and power FET, etc. We consider transistor DC chopper circuit and prove the effectiveness of our program by both the experiment and simulation.

• Progress in Superconductivity and Cryogenics
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• v.7 no.1
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• pp.17-20
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• 2005

We has designed, fabricated, and measured a Single flux quantum (SFQ) toggle flip-flop (TFF). The TFF is widely used in superconductive digital electronics circuits. Many digital devices, such as frequency counter, counting ADC and program counter be used TFF Specially, a program counter may be constructed based on TFF We have designed the newly TFF and obtained high bias margins on test. In this work, we used two circuit simulation tools, WRspice and Julia, as circuit optimization tools. We used XIC for a layout tool. Newly designed TFF had minimum bias margins of +/- $37\%$ and maximum bias margins of +/-$37\%$(enhanced from +/- $37\%$). The designed circuits were fabricated by using Nb technology The test results showed that the re-optimized TFF operated correctly on 100kHz and had a very wide bias margins of +/- $53\%$.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.11a
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• pp.23-27
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• 2000

Simultaneous Switching Noise (SSN) propagated through parallel power and ground planes in high-speed multilayer printed circuit boards (PCBs) causes malfunction of both digital and analog circuits. To reduce SSN, decoupling capacitors are generally used in the PCBs. In this paper, we improve the equivalent circuit model of decoupling capacitor in high-frequency range to analyze the effect of SSN reduction accurately. The analysis is performed by the microwave and RF design system (MDS) method and the finite difference time domain (FDTD) method. We compared the results by the ideal capacitor model with those by the proposed model.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2622-2624
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• 2002

This paper presents a virtual laboratory system which can be creating efficiencies in the learning process. The proposed virtual laboratory system for digital logic circuits provides interactive learning environment under which the multimedia capabilities of world-wide web can be enhanced. The virtual laboratory system is implemented to describe the on-campus laboratory, the learners can obtain similar experimental data through it. The virtual laboratory system is composed of four important components: principle classroom simulation classroom, virtual experiment classroom and management system. The database connectivity is made by PHP and the virtual laboratory environment is set up slightly differently for each learner. Learning efficiencies as well as faculty productivity are increased in this innovative teaching and learning environment.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.3
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• pp.68-76
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• 1994

In the automatic transistor sizing with computer for optimizing delay and the chip area of CMOS digital circuits, conventionally either a mathematical method or a heuristic method has been used. In this paper, we present a new method of transistor sizing, a sort of combination of the above two methods, in which the mathematical method is used for sizing of critical paths and the heuristic method is used for desizing of non-critical paths. In order to reduce the overall problem dimension, a basic block called an extended stage is introduced which includes a basic stage, parallel transistors and complementary part. Optimization for multiple critical paths is formulated as a problem of area minimization subject to delay constraints and is solved by the augmented Lagrange multiplier method. The transistor sizes along non-critical paths are decreased successively without affecting the critical path delay times. The proposed scheme was successfully applied to several test circuits.

• Korean Journal of Optics and Photonics
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• v.10 no.3
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• pp.259-264
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• 1999

The relationship is derived for color CRT display system between the spectral radian existence emitted and digital inputs. The amount of spectral radiant existence depends on the characteristics of the video board, electric circuits, and CRT as well as digital inputs. Especially, the function of this relationship changes as the amplifier gain and offset voltage of electric circuits. In this study, we set the test display system on the optimum state which satisfies gun independence characteristics by using the contrast and the brightness controls of display. Temporal stability, special uniformity, and color distinction of CRT display system are evaluated at the optimum state. Also contrasts in dark room and illuminated room are compared.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.05a
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• pp.419-423
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• 2004

This paper shows a new concept of digital power meter based on the optical sensing technique. The digital power meter with isolate IC so called Photocoupler is designed and implemented. The system composed of power and analong interface circuits, micro-controller and LCD display circuits. The most errors in power meter happen on measurement and calculation process for load voltages and currents. The suggested method on this paper is to use no noise sensor and PIC microprocessor. The results of simple test for power meter prototype are showed a nearly similar date to commercial product.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.03b
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• pp.3-3
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• 2010

The Characteristics of Digital Vterbi Decoder utilizing the analog parallel processing circuit technology is proposed. The Analog parallel structure of the viterbi decoder acted by a replacement of the conventional digital viterbi Decoder is progressing fastly. The proposed circuits design han, low distortion, high accuracy over the previous implementation and dynamic programming.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.837-840
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• 2007

We propose a novel digital driving method for AM-OLED (Active Matrix-Organic Light Emitting Diode) display. Proposed method modulates $V_{DD}$ so that luminance may be weighted in accordance with the bit significance. We can increase the minimum emission time or slower scan circuits are applicable by using proposed method.