• Journal of the Korean Society of Safety
• /
• v.12 no.3
• /
• pp.60-66
• /
• 1997

In this paper, a moving object surveillance system, which can extract moving object in real-time, using image subtraction method is described. This technique based on the novelty filter having the structure of neural network associative memory. Digital arithmetic and timing control parts were composed of hardwired controller to treat two-dimensional massive image information. SRAMS having 20 ns access time were used for the image buffer that has high speed write/read property. Image extraction algorithm is discussed and supported by simulation and experiments.

• 한국초전도학회:학술대회논문집
• /
• v.14
• /
• pp.55-55
• /
• 2004

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.6B
• /
• pp.727-735
• /
• 2001

본 논문은 8-VSB Advanced Digital TV용으로 사용할 수 있도록 ATSC(Advanced Television Standard Committee)의 규약을 만족시키도록 구현한 Reed Solomon 디코더에 대하여 기술한다. 구현된 RS Decoder는 공유된 Tree 구조의 Arithmetic 블록을 사용하여 종래의 기술보다 더 효율적인 연산기 구조를 제안하였으며 빠른 에러 탐지와 정정 시간으로 인한 FIFO의 사용갯수와 Latency Time을 크게 감소시킨 개선된 구조를 제안한다. 일반적으로 2N+A만큼의 Latency Time과 FIFO 개수를 N+A 만큼으로 감소시켰다. 이 RS 디코더는 Verilog HDL로 설계되었고 Synopsys Design Compiler에 의해 합성되었다.

• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.195-198
• /
• 2000

It is possible to perform the digital fuzzy logical high-speed and high-precision computation by the use of redundantly-represented binary positive-digit number arithmetic operation. In this paper, as basic operation circuits in the fuzzy logic new voltage-mode 4-valued binary parallel processing operation circuits using positive redundantly-expressed binary-coded numbers is discussed.

• Proceedings of the KIEE Conference
• /
• 2005.07b
• /
• pp.924-926
• /
• 2005

This paper presents an excellence start-up performance drive system of Switched Reluctance Motor(SRM) for hoist. At first, the SRM design method of Hoist drive is expounded, and suitable Digital control arithmetic of SRM Hoist drive is advanced in the paper. Finally, some correlative experimentation has been finished, and the SRM Hoist drive has been confirmed in the experimentation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.2
• /
• pp.820-822
• /
• 2005

We have designed a 32-bit microprocessor with fixed point digital signal processing functionality. This processor, combines both general-purpose microprocessor and digital signal processor functionality using the reduced instruction set computer design principles. It has functional units for arithmetic operation, digital signal processing and memory access. They operate in parallel in order to remove stall cycles after DSP or load/store instructions, which usually need one or more issue latency cycles in addition to the first issue cycle. High performance was achieved with these parallel functional units while adopting a sophisticated five-stage pipeline stucture.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.12 no.4
• /
• pp.309-324
• /
• 1987

In recent years has been an increasing interest with respect to using the discrete cosine transform(DCT) of which performance is found close to that of the Karhumen-Loeve transform, known to be optimal in the area of digital image processing for tha purpose of the image data compression. Among most of reported algorithms aimed at lowering the coputation complexity. Chen's algorithm is is found to be most popular, Recently, Lee proposed a now algorithm of which the computational complexity is lower than that of Chen's. but its performance is significantly degraded by FWL(Finite-Word-Lenght) effects as a result of employinga a fixed-poing arithmetic. In this paper performance evaluation of these two algorithms and error analysis of FWL effect are described. Also a scaling technique which we call Up & Down-scaling is proposed to allevaiate a performance degradation due to fixed-point arithmetic. When the 16x16point 2DCT is applied on image data and a 16-bit fixed-point arithmetic is employed, both the analysis and simulation show that is colse to that of Chen's.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.9
• /
• pp.11-20
• /
• 1998

High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

• Journal of Broadcast Engineering
• /
• v.8 no.3
• /
• pp.259-267
• /
• 2003

In this paper, we propose a media processor to provide interactive services in mobile multimedia broadcasting environments. The proposed system Is designed to support various functionalities, such as generation of MPEG-4 IOD (Initial Object Descriptor)/OD(Object Descriptor)/BIFS (Binary Format for Scene) data, encapsulation of MPEG-4 AVC (Advanced Video Coding)/BSAC (Bit Sliced Arithmetic Coding) stream and generated IOD/OD/BIFS data into SL (Sync Layer) packet, packetization of SL packet into TS (Transport Stream) packet and multiplexing. The proposed media processor can provide MPEG-4 based interactive services for users.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.33B no.1
• /
• pp.153-160
• /
• 1996

In this paper, we propose an efficient digital architecture for the discrete-time cellular neural networks (DTCNN's). DTCNN's have the locality and the translation invariance in the templates which determine the patterns of the connection between the cells. Using distributed arithmetic (DA) and the characteristics of DTCNN, we propose a simple implementation of DTCNN. The bus width in the cell-to-cell interconnection is reduced to one bit because of DA's bitwise operation. We implemented the reconfigurable architecture of DTCNN using programmable FPGA.