• 제목/요약/키워드: digital arithmetic

검색결과 154건 처리시간 0.029초

Real-time Implementation of an Identifier for Nonstationary Time-varying Signals and Systems

  • Kim, Jong-Weon;Kim, Sung-Hwan
    • The Journal of the Acoustical Society of Korea
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    • 제15권3E호
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    • pp.13-18
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    • 1996
  • A real-time identifier for the nonstationary time-varying signals and systems was implemented using a low cost DSP (digital signal processing) chip. The identifier is comprised of I/O units, a central processing unit, a control unit and its supporting software. In order t estimate the system accurately and to reduce quantization error during arithmetic operation, the firmware was programmed with 64-bit extended precision arithmetic. The performance of the identifier was verified by comparing with the simulation results. The implemented real-time identifier has negligible quantization errors and its real-time processing capability crresponds to 0.6kHz for the nonstationary AR (autoregressive) model with n=4 and m=1.

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A 3.3V 10BIT CURRENT-MODE FOLDING AND INTERPOLATING CMOS AJ D CONVERTER USING AN ARITHMETIC FUNCTIONALITY

  • Chung, Jin-Won;Park, Sung-Yong;Lee, Mi-Hee;Yoon, Kwang-Sub
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 ITC-CSCC -2
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    • pp.949-952
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    • 2000
  • A low power 10bit current-mode folding and interpolating CMOS analog to digital converter (ADC) with arithmetic folding blocks is presented in this paper. A current-mode two-level folding amplifier with a high folding rate (FR) is designed not only to prevent ADC from increasing a FR excessively, but also to perform a high resolution at a single power supply of 3.3V The proposed ADC is implemented by a 0.6${\mu}$m n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of ${\pm}$0.5LSB, an integral nonlinearity (INL) of ${\pm}$1.0LSB

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UTLIZATION OF FUZZY AND VOLETTRA ALGORITHM FOR 3D BATHYMETRY SIMULATION FROM TOPSAR POLARISED DATA

  • Marghany, Maged;Hussien, Mohd. Lokman
    • 대한원격탐사학회:학술대회논문집
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    • 대한원격탐사학회 2003년도 Proceedings of ACRS 2003 ISRS
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    • pp.432-434
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    • 2003
  • The main objective of this research is to utilize the parallel Fuzzy arithmetic for constructing ocean bathymetry from polarized remote sensing data such as TOPSAR image. In doing so, the parallel library for Fuzzy arithmetic has been developed. Three- dimensional surface modeling consisted of Volettra model, non-linear model which construct a global topological structure between the data points, used to support an approximation of real surface. The output of the parallel library was a digital terrain model for bathymetry along the coastal waters of Kuala Terengganu Malaysia. This paper describes the principles behind the Fuzzy algorithm, indicates for what type of application it might be useful, notes on the accuracy and gives an example of an application.

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SDR기반 디지털 위성 트랜스폰더를 위한 가변 표본화율의 재귀 연산 구조 (A Variable Sample Rate Recursive Arithmetic Half Band Filter for SDR-based Digital Satellite Transponders)

  • 백대성;임원규;김종훈
    • 한국통신학회논문지
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    • 제38A권12호
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    • pp.1079-1085
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    • 2013
  • 위성 트랜스폰더의 설계에 있어서 위성체의 제한된 전원자원으로 인해 연산 알고리즘의 최소화와 하드웨어 구현에 필요한 연산 및 논리 자원의 최소화가 필수적이다. 아울러 위성의 환경에 따라 다양한 대역폭에 대한 효율적 신호처리가 요구되는데 이러한 조건들은 SDR기반의 디지털 방식 구현에 적합하다. 본 논문에서는 SDR 기반의 위성 트랜스폰더 수신부에서 반송파와 레인징 및 Command 부밴드 신호에 대해 각각의 대역과 데이터율을 가변적으로 선택 할 수 있는 하향 표본화기를 제안하였다. 제안된 하향표본화기는 한 개의 하프밴드 필터로부터 재귀적 연산구조를 통해 다수의 임의의 $2^M$-하향 표본화된 신호를 얻을 수 있으며, 연산량 및 구현에 따르는 논리자원을 최소화 할 수 있다. 또한 재귀적 연산 하드웨어 구현을 위한 알고리즘과 함께 하향표본화에 따르는 대역평탄도 및 에일리어싱을 분석하고 이를 FPGA 실험을 통하여 동작 및 성능을 입증하였다.

랜덤 위상 마스크와 2-단계 위상 천이 디지털 홀로그래피를 이용한 이진 영상 이중 암호화 (Double Encryption of Binary Image using a Random Phase Mask and Two-step Phase-shifting Digital Holography)

  • 김철수
    • 한국멀티미디어학회논문지
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    • 제19권6호
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    • pp.1043-1051
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    • 2016
  • In this paper, double encryption technique of binary image using random phase mask and 2-step phase-shifting digital holography is proposed. After phase modulating of binary image, firstly, random phase mask to be used as key image is generated through the XOR operation with the binary phase image. And the first encrypted image is encrypted again through the fresnel transform and 2-step phase-shifting digital holography. In the decryption, simple arithmetic operation and inverse Fresnel transform are used to get the first decryption image, and second decryption image is generated through XOR operation between first decryption image and key image. Finally, the original binary image is recovered through phase modulation.

소형 디지털 카메라의 손떨림 보정 기능을 위한 임베디드 제어 시스템의 구현 (Implementation of an Embedded Image Stabilization Control System for a Small Digital Camera)

  • 문정호;정수열
    • 제어로봇시스템학회논문지
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    • 제13권12호
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    • pp.1160-1166
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    • 2007
  • This paper presents the design and implementation of an embedded image stabilization control system for a mobile phone with a built-in camera. Image stabilization is a family of techniques for reducing image blur resulting from minute camera shake due to hand-held shooting, thereby allowing the use of shutter speeds slower than values normally required to obtain sharp images. A mechanical image stabilizer mechanism developed for a camera mobile phone is introduced and a digital control system as a part of the image stabilization system is designed and implemented on an 8-bit microcontroller with integer arithmetic in C. This paper focuses primarily on issues that need to be taken into consideration for fixed-point implementation of the digital controller. Several experimental results are presented to demonstrate the performance of the implemented image stabilization control system.

이선 가입자에서의 기본대역 전송을 위한 새로운 디지탈 반향제법방식 (A New digital Echo Canceler for Baseband Data Transmission in Two-Wire Subscriber Lines)

  • 황찬식;심영석
    • 대한전자공학회논문지
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    • 제21권2호
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    • pp.24-28
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    • 1984
  • 이선 선로를 통한 full-duplex 데이타 전송에 있어서 hybrid-coupler의 불완전한 송·수신에 따른 반향신호는 데이타 검출에 큰 장애가 되고 있다. 본 논문에서는 산술평균에 의한 반향신호 추정법을 제시하고 이를 적응 디지탈 필터에 의한 추정법과 이론적 해석 및 컴퓨터 시뮬레이션을 통해 비교하였다. 양자화 효과를 고려한 이론적인 해석 결과 산술평균 추정을 사용한 반향제거는 hardware 구성이 간단하면서도 수렴이 매우 빠름을 밝혔다. 특히 제시된 방식은 선로 감쇠량에 관계없이 반향신호를 정해진 시간내에 충분히 제거할 수 있다.

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하이브리드형 선형 펄스모터의 디지털 서보 제어기 설계 (Design of Digital Servo Controller for Hybrid Linear Pulse Motor)

  • 배동관;안재영;김광헌
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2003년도 춘계전력전자학술대회 논문집(1)
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    • pp.389-392
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    • 2003
  • A use of micro processor having H-com functions is gradually increased, and this paper describes the digital servo controller applied to linear pulse motor The TMS320LF2407, made by TI(Texas Instruments Co.), is used as a arithmetic unit in control circuit, designed f3r motor drive and available for the implement of high performance and miniaturization. Also, it can allow the sufficient debugging and downloading into control board for independent operation. A current control in order to carry out a position control is of a digital current control mode, and its implement confirmed the servo control performance of position control.

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원자력발전소 디젤발전기 디지털 다중화 여자시스템 개발 및 적용 (The Development of Digital Excitation Control System for Diesel Generator of Nuclear Power Plant and Its Application)

  • 이주현;임익헌;신만수;정태원
    • 전기학회논문지
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    • 제59권8호
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    • pp.1449-1455
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    • 2010
  • The excitation control system of an emergency diesel generator is classified as a kind of safety-related system. Compared with other control systems in a power plant, this system is required to be more reliable and have better performance. In this paper, the digital multi-redundant excitation system for a diesel generator was proposed. The signal processing system of the proposed system makes high speed signal processing and arithmetic in excitation control possible. The improved soft start algorithm and multiple PI parameters adaptation considering the diesel generator characteristics were implemented in the proposed system. The developed system was applied to a nuclear power plant successfully.

DSP의 DMA 제어기를 이용한 변압기용 디지털 보호계전기의 성능향상 (Efficiency Improvement of Digital Protective Relay for Power Transformer Using DMA Controller of DSP)

  • 권기백;서희석;신명철
    • 대한전기학회논문지:전력기술부문A
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    • 제52권11호
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    • pp.647-654
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    • 2003
  • As electrical power system has become complicated and enlarged to cope with the increasing electric demand, it has to be expected that higher speed, higher reliability, higher function and higher arithmetic ability in protective relay should be realized. Therefore, in this papers, by hardware design and implementation used DMA controller that transfer blocks of data to any location in the memory map without interfering with CPU operation, CPU utilization is increased effectively, as a result it made possible to implement multi-function digital protective relay which has high trust and high function of protection as well as control and metering for power transformers using single processor(DSP).