• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.3
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• pp.13-18
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• 2010

This work proposes and characterizes switched-capacitor type cyclic digital-to-analog converter for display data driving. The proposed digital-to-analog converter composes simple structure, and can be implemented for low-power, small area display driver ICs. By circuit level simulations, it is verified that the op-amp input referred offset is attenuated at the DAC output and the circuit performance is robust at 0.5% of capacitor mismatch.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.818-819
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• 2013

This paper propose a contents security technique for digital holographic display service. Digital holographic video system assumes the existing service frame for 2-dimensional or 3-dimensional video, which includes data acquisition, processing, transmission, reception, and reconstruction. In this paper, we perform the encryption of RGB image and depth-map for such a system. The experimental results showed that encrypting only 0.048% of the entire data was enough to hide the constants of the RGB image and depth-map.

• Journal of Forest and Environmental Science
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• v.33 no.3
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• pp.187-196
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• 2017

The use of unmanned aerial vehicles (UAV) for the estimation of tree height is gaining recognition. This study aims to assess the effectiveness of tree height estimation of Pinus densiflora Sieb. et Zucc. and Pinus koraiensis Sieb. et Zucc. using digital surface model (DSM) generated from UAV-acquired imageries. Images were taken with the $Trimble^{(R)}$ UX5 equipped with Sony ${\alpha}5100$. The generated DSM, together with the digital elevation model (DEM) generated from a digital map of the study areas, were used in the estimation of tree height. Field measurements were conducted in order to generate a regression model and carry out accuracy assessment. The obtained coefficients of determination (R2) and root mean square error (RMSE) for P. densiflora (R2=0.71; RMSE=1.00 m) and P. koraiensis (R2=0.64; RMSE=0.85 m) are comparable to the results of similar studies. The results of the paired two-tailed t-test show that the two tree height estimation methods are not significantly different (p-value=0.04 and 0.10, alpha level=0.01), which means that tree height estimation using UAV imagery could be used as an alternative to field measurement.

• Journal of Korea Game Society
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• v.11 no.6
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• pp.61-70
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• 2011

In this paper, we propose a defense NPC control model in the soccer game by applying the Decision Tree learning algorithm. The proposed model extracts the direction patterns and the action patterns generated by many soccer game users, and applies these patterns to the Decision Tree learning algorithm. Then, the proposed model decides the direction and the action according to the learned Decision Tree. Experimental results show that the proposed model takes some time to learn the Decision Tree while the proposed model takes 0.001-0.003 milliseconds to decide the direction and the action based on the learned Decision Tree. Therefore, the proposed model can control NPC in the soccer game system in real time. Also, the proposed model achieves higher accuracy than a previous model (Letia98); because the proposed model can utilize current state information, its analyzed information, and previous state information.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2065-2069
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• 2014

The DAC-7512E is a 12-bit digital to analog converter that is low power and a single package with internal buffers. The DAC-7512E takes up minimal PCB area for applications of space power electronics design. The spacecraft mass is a crucial point considering spacecraft launch into space. Therefore, we have performed a TID test for the DAC-7512E 12-bit serial input digital to analog converter to reduce the spacecraft mass by using a low-level Gamma-ray irradiator with $Co^{60}$ gamma-ray sources. The irradiation with $Co^{60}$ gamma-rays was carried out at doses from 0 krad to 100 krad to check the error status of the device in terms of current, voltage and bit error status during conversion. The DAC-7512E 12-bit serial digital to analog converter should work properly from 0 krad to 30 krad without any error.

• 전자공학회논문지 IE
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• v.47 no.2
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• pp.1-7
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• 2010

This paper presents a low power digital PLL architecture and design for implementation of the PLL-based frequency synthesizers. In the proposed architecture, a wide band digital logic quadricorrelator is used for preliminary frequency detector and a narrow band digital logic quadricorrelator is used for final DCO control. Also, a circuit technique for reducing leakage current is adopted in order to minimize the standby mode power consumption of the deactivated block. The proposed digital PLL is designed and verified by MyCAD with MOSIS 1.8V $0.35{\mu}m$ CMOS technology, and the simulation results show that the power consumption can be lowered by more than 20%.

• ETRI Journal
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• v.29 no.1
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• pp.99-102
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• 2007

The channel level difference (CLD) is a main parameter in the reference model 0 (RM0) for MPEG Surround. Nevertheless, the CLD quantization method in the RM0 has problems such as the lack of theoretical background and inappropriate quantization levels. In this letter, a new CLD quantization method is proposed based on the virtual source location information which has strength in the quantization process. From experimental results, it is confirmed that the proposed scheme greatly reduces the quantization distortions measured in dB and degrees without any additional complexity.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.334-341
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• 2015

This research outlines the design of a HR-TDC (High Resolution Time-to-Digital Converter) for high data rate communication systems using a $0.18{\mu}m$ CMOS process. The coarse-fine architecture has been adopted to improve the resolution of the TDC. A two-stage vernier time amplifier (2S-VTA) was used to amplify the time residue, and the gain of the 2S-VTA was larger than 64. The error during time amplification was compensated using two FTDCs (Fine-TDC) with their outputs. The resolution of the HR-TDC was 0.15 ps with a 12-bit output and the power consumption was 4.32 mW with a 1.8-V supply voltage.

• ETRI Journal
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• v.35 no.4
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• pp.638-643
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• 2013

This paper presents a 5-bit digital step attenuator (DSA) using a commercial 0.18-${\mu}m$ silicon-on-insulator (SOI) process for the wideband phased array antenna. Both low insertion loss and low root mean square (RMS) phase error and amplitude error are achieved employing two attenuation topologies of the switched path attenuator and the switched T-type attenuator. The attenuation coverage of 31 dB with a least significant bit of 1 dB is achieved at DC to 20 GHz. The RMS phase error and amplitude error are less than $2.5^{\circ}$ and less than 0.5 dB, respectively. The measured insertion loss of the reference state is less than 5.5 dB at 10 GHz. The input return loss and output return loss are each less than 12 dB at DC to 20 GHz. The current consumption is nearly zero with a voltage supply of 1.8 V. The chip size is $0.93mm{\times}0.68mm$, including pads. To the best of the authors' knowledge, this is the first demonstration of a low phase error DC-to-20-GHz SOI DSA.

• Korean Journal of Digital Imaging in Medicine
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• v.6 no.1
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• pp.24-30
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• 2003

Flat-panel detector(FPD) is the driving force for realizing the next gene ration of x-ray system. In this study, we developed amorphous selenium(a-Se) based flat-panel digital X-ray detector(DXD) for radiography. The prototype detector consists of an amorphous selenium layer and a thin-film transistor(TFT) array. Comparing to other papers1)-4), optimization of amorphous selenium and progress of evaporation were similar. The pixel pitch of fabricated detector was $139{\mu}m$, fill factor was 86%, and the size was 14"${\times}$8.5". Hand and test bar pattern images were acquired. A high modulation transfer function(MTF) factor was obtained: 58% at 3.0 lp/mm.