• Title/Summary/Keyword: differential circuits

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A Novel CMOS Rail-to-Rail Input Stage Circuit with Improved Transconductance (트랜스컨덕턴스 특성을 개선한 새로운 CMOS Rail-to-Rail 입력단 회로)

  • 권오준;곽계달
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.12
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    • pp.59-65
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    • 1998
  • In this paper, a novel rail-to-rail input stage circuit with improved transconductance Is designed. Its excellent performances over whole common-mode input voltage Vcm range is demonstrated by circuit simulator HSPICE. The novel input stage circuit comprises additional 4 input transistors and 4 current sources/sinks. It maintains DC currents of signal amplifying transistors when one of the differential input stage circuits operates, but it reduces these currents to 1/4 when both differential input stage circuits operates, As a result, a operational amplifier with the novel circuit maintains nearly constant transconductance performance and unity-gain frequency in strong inversion region. The novel circuit allows an optimal frequency compensation and uniform operational amplifier performance over whole Vcm range.

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The design of a charge pump for the high speed operation of PLL circuits (High speed에 필요한 PLL charge pump 회로 설계 및 세부적인 성능 평가)

  • 신용석;윤재석;허창우
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.2 no.2
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    • pp.267-273
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    • 1998
  • In this paper, we designed a charge pump with a differential current switching structure and it was made of a MESFET with high speed switching Property compared with CMOSFETs. The charge pump with a differential current switching structure is analyzed about operating property of circuit in high frequency band. Also we propose a method on it's characteristics estimation. The designed circuit is simulated by HSPICE simulator, and in view of the results we think that the charge pump of this study can be used in circuits of 1 GHZ frequency band grade.

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A method for reducing the residual voltage of hybrid SPD circuit using choke coils (초크코일을 이용한 SPD 조합회로의 잔류전압 저감기법)

  • Lee, Tae-Hyung;Jo, Sung-Chul;Han, Hoo-Suk;Eom, Ju-Hong
    • Proceedings of the KIEE Conference
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    • 2006.07c
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    • pp.1488-1489
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    • 2006
  • Gas Discharge Tubes (GDTs) are widely used as surge protectors for communication applications due to their small internal capacitance. In these days, however, they are mostly used in combined configurations, because the activation voltage required to initiate the discharge process in the GDTs for sufficient amount of time can be large enough to damage surge-sensitive protected circuits. For GDTs with a considerably high initial over-voltage value, we should limit the peak voltage using a TVS or filter. As for ZnO varistors, even though their performance for voltage restriction is excellent their applications in high-frequency communication circuits have been limited because of higher internal capacitance when compared to the GDTs. In order to develop a surge protector for communication applications by taking advantages of these two devices, we built a combination circuit that connects a GDT and a ZnO varistor along with a choke coil in common and differential modes. We describe how the applied SPDs operate in protection process steps with the actual data obtained from the residual voltage measurements at each step. The experiment results show that the surge voltage restriction with the choke coil is more effective in differential mode than in common mode.

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A Method for Reducing the Residual Voltage of Hybrid SPD Circuit Using Choke Coil (초크코일을 이용한 SPD 조합회로의 잔류전압 저감기법)

  • Cho, Sung-Chul;Eom, Ju-Hong;Lee, Tae-Hyung
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.21 no.8
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    • pp.96-101
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    • 2007
  • Gas Discharge Tubes (GDTs) are widely used as surge protectors for communication applications due to their small internal capacitance. In these days, however, they are mostly used in combined configurations, because the sparkover voltage required to initiate the discharge process in the GDTs and the time taken for arc formation process can be large enough to damage to sensitive circuits. For GDTs with a considerably high initial residual voltage, we should limit the peak voltage using a TVS or filter. We made a hybrid SPD circuits of common-mode type and differential-mode type with the filter using common-mode choke. Also, we applied lightning impulse voltage and ring wave voltage which frequency bandwidth are different each other and verified the characteristics of hybrid SPD circuits according to waveshapes. We describe how the applied SPDs operate in protection process steps with the actual data obtained from the residual voltage measurement at each step. The experiment results show that the surge voltage reduction with the choke coil is more effective in differential-mode circuit than in common-mode circuit.

Developed of non-differential pulse detection (비미분형 맥동검출변환기 개발)

  • Kim, H.K.;Han, S.H.;Lee, Y.D.;Park, Y.B.;Huh, W.
    • Proceedings of the IEEK Conference
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    • 1998.06a
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    • pp.573-576
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    • 1998
  • In this paper, we devised pulse detection transducer that has non-differential characteristics for pulse detection on chongu arterial. The transducer consist of load cell and driving electronic circuits. Load cell consist of cantilever and two metal film strain gauge. The pressure signal from chongu artery is delivered to load cell using artery rider that attached to cantilever. Therefore the pressure pulse signal can obtain by the developed transducer. As the results of experiment, the developed transducer has a good linearity at pressure to voltage conversion and acan detect non-differential pulse signal from chongu artery.

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1.5Gb/s Low Power LVDS I/O with Sense Amplifier (Sense amplifier를 이용한 1.5Gb/s 저전력 LVDS I/O 설계)

  • 변영용;이승학;김성하;김동규;김삼동;황인석
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.979-982
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    • 2003
  • Due to the differential transmission technique and low voltage swing, LVDS has been widely used for high speed transmission with low power consumption. This paper presents the design and implementation of interface circuits for 1.5Gb/s operation in 0.35um CMOS technology. The interface circuit ate fully compatible with the low-voltage differential signaling(LVDS) standard. The LVDS proposed in this paper utilizes a sense amplifiers instead of the conventional differential pre-amplifier, which provides a 1.5Gb/s transmission speed with further reduced driver output voltage. Furthermore, the reduced driver output voltage results in reducing the power consumption.

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Symmetric Adiabatic Logic Circuits against Differential Power Analysis

  • Choi, Byong-Deok;Kim, Kyung-Eun;Chung, Ki-Seok;Kim, Dong-Kyue
    • ETRI Journal
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    • v.32 no.1
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    • pp.166-168
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    • 2010
  • We investigate the possibility of using adiabatic logic as a countermeasure against differential power analysis (DPA) style attacks to make use of its energy efficiency. Like other dual-rail logics, adiabatic logic exhibits a current dependence on input data, which makes the system vulnerable to DPA. To resolve this issue, we propose a symmetric adiabatic logic in which the discharge paths are symmetric for data-independent parasitic capacitance, and the charges are shared between the output nodes and between the internal nodes, respectively, to prevent the circuit from depending on the previous input data.

Low-noise fast-response readout circuit to improve coincidence time resolution

  • Jiwoong Jung;Yong Choi;Seunghun Back;Jin Ho Jung;Sangwon Lee;Yeonkyeong Kim
    • Nuclear Engineering and Technology
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    • v.56 no.4
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    • pp.1532-1537
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    • 2024
  • Time-of-flight (TOF) PET detectors with fast-rise-time scintillators and fast-single photon time resolution silicon photomultiplier (SiPM) have been developed to improve the coincidence timing resolution (CTR) to sub-100 ps. The CTR can be further improved with an optimal bandwidth and minimized electronic noise in the readout circuit and this helps reduce the distortion of the fast signals generated from the TOF-PET detector. The purpose of this study was to develop an ultra-high frequency and fully-differential (UF-FD) readout circuit that minimizes distortion in the fast signals produced using TOF-PET detectors, and suppresses the impact of the electronic noise generated from the detector and front-end readout circuits. The proposed UF-FD readout circuit is composed of two differential amplifiers (time) and a current feedback operational amplifier (energy). The ultra-high frequency differential (7 GHz) amplifiers can reduce the common ground noise in the fully-differential mode and minimize the distortion in the fast signal. The CTR and energy resolution were measured to evaluate the performance of the UF-FD readout circuit. These results were compared with those obtained from a high-frequency and single ended readout circuit. The experiment results indicated that the UF-FD readout circuit proposed in this study could substantially improve the best achievable CTR of TOF-PET detectors.

Design of a New CMOS Differential Amplifier Circuit (새로운 구조를 갖는 CMOS 자동증폭회로 설계)

  • 방준호;조성익;김동용;김형갑
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.18 no.6
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    • pp.854-862
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    • 1993
  • All of the CMOS analog and analog-digital systems have composed with several basic circuits, and among them, a important block, the amplifier part can affect the system's performance, Therefore, according to the uses in the system, the amplifier circuit have designed as various architectures (high-gain, low-noise, high-speed circuit, etc...). In this paper, we have proposed a new CMOS differential amplifier circuit. This circuit is differential to single ended input stage comprised of CMOS complementary gain circuits having internally biasing configurations. These architectures can be achieved the high gain and reduced the transistors for biasing. As a results of SPICE simulation with the standard $1.5{\mu}m$ processing parameter, the gain of the proposed circuit have a doubly value of the typical circuit's while maintaining other characteristics(phase margin, offset, etc...). And the proposed circuit is applicated in a simple CMOS comparator which has the settling time in 7nsec(CL=1pF) and the igh output swing $({\pm}4.5V)$.

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A Chip Design of Body Composition Analyzer (체성분 분석용 칩 설계)

  • Bae, Sung-Hoon;Moon, Byoung-Sam;Lim, Shin-Il
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.3 s.357
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    • pp.26-34
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    • 2007
  • This Paper describes a chip design technique for body composition analyzer based on the BIA (Bioelectrical Impedance Analysis) method. All the functions of signal forcing circuits to the body, signal detecting circuits from the body, Micom, SRAM and EEPROMS are integrated in one chip. Especially, multi-frequency detecting method can be applied with selective band pass filter (BPF), which is designed in weak inversion region for low power consumption. In addition new full wave rectifier (FWR) is also proposed with differential difference amplifier (DDA) for high performance (small die area low power consumption, rail-to-rail output swing). The prototype chip is implemented with 0.35um CMOS technology and shows the power dissipation of 6 mW at the supply voltage of 3.3V. The die area of prototype chip is $5mm\times5mm$.