• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.421-422
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• 2008

In this paper, CMOS RF front-end circuits for an L1/L5 dual-band global positioning system (GPS)/Galileo receiver are designed in $0.13\;{\mu}m$ CMOS technology. The RF front-end circuits are composed of an RF single-to-differential low noise amplifier, an RF polyphase filter, two down-conversion mixers, two transimpedance amplifiers, a IF polyphase filter, four de-coupling capacitors. The CMOS RF front-end circuits provide gains of 43 dB and 44 dB, noise figures of 4 dB and 3 dB and consume 3.6 mW and 4.8 mW from 1.2 V supply voltage for L1 and L5, respectively.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.93-96
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• 2001

A design methodology of analog circuits for a CMOS stereo 16-bit Δ$\Sigma$ DAC which are suitable for the digital audio applications is described. The limitations of Δ$\Sigma$ DAC exist in the performance of the 1-bit DAC and that of the smoothing filter. The proposed architecture for analog circuits contains the buffer between the digital modulator and the following analog stage and adopts the SCF (switched capacitor filter) and DSC (differential-to-single converter) scheme. In this paper, a guide line for the selection of the filter type for the SCF design in the Δ$\Sigma$ DAC is suggested through the analytical approaches.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.615-616
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• 2006

Nowadays, the need of multi-mode/multi-band transceiver is rapidly increasing, so we design a direct conversion RF front-end for multi-mode/multi-band receiver that support WCDMA/CDMA2000/WIBRO standard. It consists of variable gain reconfigurable LNA and single input double balanced Mixer and complementary differential LC Oscillator. The circuit is implemented in 0.18 um RF CMOS technology and is suitable for low-cost mode/multi-band.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.1
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• pp.108-112
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• 2001

Heart sound contains rich information regarding the dynamics of the heart and the auscultation has been a first choice of routine procedures for diagnosis of the heart. However, heart sounds captured using a conventional stethoscope are not often loud or clear enough for doctors to precisely classify their characteristics, especially, under the noisy environments of the hospital. A simple auscultation device that removed shortcomings of the conventional stethoscope was constructed in the study. The device employed a polymer based adherent differential output sensor which was on contact with skin through a coupling medium and appropriated electronic circuits for signal amplification and conditioning An ordinary headphone is taken to hear the captured heart sounds and the volume can be adjusted to hear well. It is also possible that the device sends the captured heart sound signals to a PC where the signals are further processed and viualized.

• Journal of Astronomy and Space Sciences
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• v.27 no.3
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• pp.239-244
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• 2010

A simulation for the design of a $90^{\circ}$ differential phase shifter aimed toward Korean VLBI Network (KVN) 129 GHz band polarizer is described in this paper. A dual-circular polarizer for KVN 129 GHz band consists of a $90^{\circ}$ differential phase shifter and an orthomode transducer. The differential phase shifter is made up of a square waveguide with two opposite walls loaded with corrugations. Three-dimensional electromagnetic simulation has been performed to predict the $90^{\circ}$ differential phase shifter's characteristics. The simulation for the differential phase shifter shows that the phase shift is $90^{\circ}{\pm}3.3^{\circ}$ across 108-160 GHz and the return losses of two orthogonal modes are better than -30 dB within the design frequency band. According to the simulation results the calculated performance is quite encouraging for KVN 129 GHz band application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.714-723
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• 2003

An effective technique to increase the signal swing and reduce noise is to use fully-differential -circuits. However, design of a common-mode feedback (CMFB) circuit that stabilizes the common-mode output level is essential. In this paper, a general description is given to fully-differential amplifiers with their CMFB loops, then a new error amplifier that is just composed of transistors and stabilizes the DC output level is proposed. We designed a simple and efficient bias circuit that allows the stability and maximum input swing. Simulation result shows the enhanced phase margin and increased differential-mode input swing with a proposed error amplifier.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.4
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• pp.602-610
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• 1993

The DDA of new active element and the DDA differential integrator are designed. The DDA can be improved matching problems of external elements in op-amp application circuits. The design of DDA is used the transconductance element, differential pair and $2{\mu}m$ design rule. In order to evaluate the performance of the CMOS DDA, we simulated the DDA voltage inverter and the DDA level shifter using the designed CMOS DDA. Furthermore, the grounded resistor and the differential integrator is designed using the CMOS DDA and we found that its characteristics are agreed to OP-AMP differential integrator's. We performed the layout of the CMOS DDA and DDA differential integrator with MOSIS $2{\mu}m$ CMOS technology.

• Journal of Power Electronics
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• v.15 no.2
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• pp.346-355
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• 2015

On the basis of the conventional PID control algorithm, a modified adaptive PID (MA-PID) control algorithm is presented to improve the steady-state and dynamic performance of closed-loop systems. The proposed method has a straightforward structure without excessively increasing the complexity and cost. It can adaptively adjust the values of the control parameters ($K_p$, $K_i$ and $K_d$) by following a new control law. Simulation results show that the line transient response of the MA-PID is better than that of the adaptive digital PID because the differential coefficient $K_d$ is introduced to changes. In addition, experimental results based on a FPGA indicate that the MA-PID control algorithm reduces the recovery time by 62.5% in response to a 1V line transient, 50% in response to a 500mA load transient, and 23.6% in response to a steady-state deviation, when compared with the conventional PID control algorithm.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.9
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• pp.3266-3285
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• 2014

With limited computing and storage resources, many network applications of encryption algorithms require low power devices and fast computing components. CHESS-64 is designed by employing simple key scheduling and Data-Dependent operations (DDO) as main cryptographic components. Hardware performance for Field Programmable Gate Arrays (FPGA) and for Application Specific Integrated Circuits (ASIC) proves that CHESS-64 is a very flexible and powerful new cipher. In this paper, the security of CHESS-64 block cipher under related-key differential cryptanalysis is studied. Based on the differential properties of DDOs, we construct two types of related-key differential characteristics with one-bit difference in the master key. To recover 74 bits key, two key recovery algorithms are proposed based on the two types of related-key differential characteristics, and the corresponding data complexity is about $2^{42.9}$ chosen-plaintexts, computing complexity is about $2^{42.9}$ CHESS-64 encryptions, storage complexity is about $2^{26.6}$ bits of storage resources. To break the cipher, an exhaustive attack is implemented to recover the rest 54 bits key. These works demonstrate an effective and general way to attack DDO-based ciphers.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.1
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• pp.1-7
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• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.