• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.1-7
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• 2020

The backside metallization process is typically used to attach a chip to a lead frame for semiconductor packaging because it has excellent bond-line and good electrical and thermal conduction. In particular, the backside metal with the Ag/Sn/Ag sandwich structure has a low-temperature bonding process and high remelting temperature because the interfacial structure composed of intermetallic compounds with higher melting temperatures than pure metal layers after die attach process. Here, we introduce a die attach process with the Ag/Sn/Ag sandwich structure to apply commercial semiconductor packages. After the die attachment, we investigated the evolution of the interfacial structures and evaluated the shear strength of the Ag/Sn/Ag sandwich structure and compared to those of a commercial backside metal (Au-12Ge).

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.11a
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• pp.437-440
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• 2000

Composite material consists of more than two materials and make various kinds of composite materials by combining different single materials. Copper clad aluminum composite material is composed of Al and Cu, and it has already been put to practical use in Europe because of its economic benefits. This paper presents the interface bonding according to the variation of extrusion ratio and semi-angle die by observing the interface between Cu and Al using metal microscope. By that result, we can predict the conditions of the interface bonding according to the extruding conditions.

• Journal of the Korean Society for Precision Engineering
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• v.32 no.9
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• pp.799-805
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• 2015

The further development of information, communication and digital media technologies requires the use of advanced, miniaturized semiconductor chips that operate at a high frequency. Die bonding and wire bonding methods for semiconductor packaging have been replaced by direct attachment to the substrate after forming a bump on the chip. However, the height of the bump or ball is an important factor for defects during assembly. This paper proposes an algorithm to measure the height of the bumps or balls in semiconductor packaging with greater accuracy. The performance of the proposed algorithm is experimentally validated. Non-contact 3D measurements of a shiny round ball is quite difficult, and it is not easy to obtain accurate data. This paper thus proposes an optical method and technique to improve the measurement accuracy.

• Journal of Welding and Joining
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• v.20 no.4
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• pp.498-504
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• 2002

Fluxless flip chip bonding process using plasma treatment instead of flux was investigated. The effect of plasma process parameters on tin-oxide etching characteristics were estimated with Auger depth profile analysis. The die shear test was performed to evaluate the adhesion strength of the flip chip bonded after plasma treatment. The thickness of oxide layer on tin surface was reduced after Ar+H2 plasma treatment. The addition of H2 improved the oxide etching characteristics by plasma. The die shear strength of the plasma-treated Sn-Pb solder flip chip was higher than that of non-treated one but lower than that of fluxed one. The difference of the strength between plasma-treated specimen and non-treated one increased with increase in bonding temperature. The plasma-treated flip chip fractured at solder/TSM interface at low bonding temperature while the fracture occurred at solder/UBM interface at higher bonding temperature.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.43-55
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• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.65-70
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• 2014

Warpage of top packages to form thin package-on-packages was measured with progress of their process steps such as PCB substrate itself, chip bonding, and epoxy molding. The $100{\mu}m$-thick PCB substrate exhibited a warpage of $136{\sim}214{\mu}m$. The specimen formed by mounting a $40{\mu}m$-thick Si chip to such a PCB using a die attach film exhibited the warpage of $89{\sim}194{\mu}m$, which was similar to that of the PCB itself. On the other hand, the specimen fabricated by flip chip bonding of a $40{\mu}m$-thick chip to such a PCB possessed the warpage of $-199{\sim}691{\mu}m$, which was significantly different from the warpage of the PCB. After epoxy molding, the specimens processed by die attach bonding and flip chip bonding exhibited warpages of $-79{\sim}202{\mu}m$ and $-117{\sim}159{\mu}m$, respectively.

• Journal of Ocean Engineering and Technology
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• v.13 no.3 s.33
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• pp.77-82
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• 1999

The compleete joining method for dissimilar hot die punch materials and its real-time evaluation method are not available at present. Brazing method has been used for joining them, but it is known that the welded joint by the brazing has the lower bonding efficiency and reliability than the diffusion welding. The friction wleding with a diffusion mechanism in bonding was applied in this study. So, this work was carried out to determine the optimal friction welding conditions and to analyze mechanical properties of friction welded joints of hot die punch materials (STD61 for the blade part of hot die punch) to alloy steel (SCM440 for the shank park of hot die punch) such as plunger. In addition, acoustic emission test was carried out during friction welding to evaluate the weld quality.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.23 no.4
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• pp.355-360
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• 2014

Recently, the use of LED is increasing. This paper presents the new package process of thermal compression bonding using metal layered LED chip for the high power LED device. Effective thermal dissipation, which is required in the high power LED device, is achieved by eutectic/flip chip bonding method using metal bond layer on a LED chip. In this study, the process condition for the LED eutectic die bonder system is proposed by using the analysis program, and some experimental results are compared with those obtained using a DST (Die Shear Tester) to illustrate the reliability of the proposed process condition. The cause of bonding failures in the proposed process is also investigated experimentally.

• 한국금형공학회:학술대회논문집
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• 2008.06a
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• pp.209-213
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• 2008

In this work, we have proposed a method for calculating the residual stress developed during the PCB thermo-compression bonding precess. Residual stress is the most important factor that causes PCB warpage in accordance with the pattern design. In this work, a single-layed double-sided PCB, which is comprised of the dielectric (FR-4) substrate in the middle and copper cladding on the both top and bottom sides, is considered. A reference temperature, where all stress is free, is calculated by comparing the calculated and measured warapge of a PCB of which copper cladding of the top side is removed. Then, the reesidual stress values is calculated for the double-sided PCB.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.477-478
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• 2012