• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 Proceedings of 5th International Joint Symposium on Microeletronics and Packaging
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• pp.43-55
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• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.

• 전기전자학회논문지
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• 제24권4호
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• pp.1028-1033
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• 2020

기존의 동일대역 간섭저감 방법은 무선기기 사이에 물리적인 이격거리를 지정하는 것으로 이격거리를 통해서 간섭을 억제한다. 만약 무선기기에서 동일대역 간섭을 저감할 수 있다면 물리적인 이격거리에 마진을 줄 수 있고, 수신기의 동작영역을 확장시키는 효과가 있으므로 간섭 대응 및 개선에 활용도가 크다. 본 논문에서는 동일대역 아날로그 간섭저감기의 구조를 제안하였고, 제안한 아날로그 간섭저감기의 설계와 구현에 대해서 기술하였다. 아날로그 간섭저감기를 설계하기 위해서 아날로그 간섭저감기의 성능에 영향을 미치는 지연(delay) 불일치, 위상오차 그리고 지연선로의 수에 따른 간섭저감 성능을 시뮬레이션 하였다. 16개의 지연선로로 구성된 아날로그 간섭저감기를 제작하였으며, 구현한 간섭저감기는 3.32㎓의 중심주파수에서 40MHz 대역폭을 갖는 5G(NR-FR1-TM-1.1) 신호에 대해서 약 10dB의 간섭저감 성능을 갖는다. 본 논문에서 제안한 아날로그 간섭저감기는 동일대역 간섭저감기로 활용가능하다.

• 한국재료학회지
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• 제8권8호
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• pp.744-750
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• 1998

마이크로 머신 소자는 일반전자 소자와 달리 소자 자체에 미세한 기계적 구조물을 갖고 있으며, 이의 구동을 통하여 센서 또는 엑츄에이터의 기능을 갖게 된다. 이 소자들은 그 작동 요구특성에 따라 패키지의 기계적, 환경적 격리를 요구하거나 분위기조절이 요구되는 등 까다로운 패키지 특성을 필요로 한다. 또한 미세한 작동소자들로 인하여 열 및 열응력에 매우 민감하며, 패키지방법에 따라 구동부위의 작동 특성이 크게 변화할 수 있다. 본 연구에서는 마이크로 머신 소자가 패키지 상에 접촉되어 패키지 될 때, 소자의 접촉 재료 및 공정온도, 크기 등이 마이크로 머신 소자에 미치는 열응력을 연구하였다. 유한요소해석법을 사용하여 소자에 미치는 열응력과 이로 인한 마이크로머신 소자의 물리적 변형을 예측하고, 이를 통하여 마이크로 머신 소자 패키지에 최소한의 열응력을 미치는 소자접속 재료의 선별과 패키지 설계의 최적화를 이루고자 하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.469-472
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• 1999

CeO$_2$ thin films have used in wide applications such as SOI, buffer layer, antirflection coating, and gate dielectric layer. CeO$_2$takes one of the cubic system of fluorite structure and shows similar lattice constant (a=0.541nm) to silicon (a=0.543nm). We investigated CeO$_2$films as buffer layer material for nonvolatile memory device application of a single transistor. Aiming at the single transistor FRAM device with a gate region configuration of PZT/CeO$_2$ /P-Si , this paper focused on CeO$_2$-Si interface properties. CeO$_2$ films were grown on P-type Si(100) substrates by 13.56MHz RF magnetron sputtering system using a 2 inch Ce metal target. To characterize the CeO$_2$ films, we employed an XRD, AFM, C-V, and I-V for structural, surface morphological, and electrical property investigations, respectively. This paper demonstrates the best lattice mismatch as low as 0.2 % and average surface roughness down to 6.8 $\AA$. MIS structure of CeO$_2$ shows that breakdown electric field of 1.2 MV/cm, dielectric constant around 13.6 at growth temperature of 200 $^{\circ}C$, and interface state densities as low as 1.84$\times$10$^{11}$ cm $^{-1}$ eV$^{-1}$ . We probes the material properties of CeO$_2$ films for a buffer layer of FRAM applications.

• Journal of Electrical Engineering and Technology
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• 제7권4호
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• pp.501-512
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• 2012

Social welfare maximization in a double-sided auction market is performed by implementing an aggregation-based particle swarm optimization (CAPSO) algorithm for optimal placement and sizing of one Static Synchronous Series Compensator (SSSC) device. Dallied simulation results (without/with line flow constraints and without/with SSSC) are generated to demonstrate the impact of SSSC on the congestion levels of the modified IEEE 14-bus test system. The proposed CAPSO algorithm employs conventional quadratic smooth and augmented quadratic nonsmooth generator cost curves with sine components to improve the accurate of the model by incorporating the valve loading effects. CAPSO also employs quadratic smooth consumer benefit functions. The proposed approach relies on particle swarm optimization to capture the near-optimal GenCos and DisCos, as well as the location and rating of SSSC while the Newton based load flow solution minimizes the mismatch equations. Simulation results of the proposed CAPSO algorithm are compared to solutions obtained by sequential quadratic programming (SQP) and a recently implemented Fuzzy based genetic algorithm (Fuzzy-GA). The main contributions are inclusion of customer benefit in the congestion management objective function, consideration of nonsmooth generator characteristics and the utilization of a coordinated aggregation-based PSO for locating/sizing of SSSC.

• 한국복합재료학회:학술대회논문집
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• 한국복합재료학회 2005년도 춘계학술발표대회 논문집
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• pp.5-8
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• 2005

In this paper, the electromechanical displacements of curved piezoelectric actuators composed of PZT ceramic and laminated composite materials are calculated based on high performance computing technology and the optimal configuration of composite curved actuator is examined. To accurately predict the local pre-stress in the device due to the mismatch in coefficients of thermal expansion, carbon-epoxy and glass-epoxy as well as PZT ceramic are numerically modeled by using hexahedral solid elements. Because the modeling of these thin layers increases the number of degrees of freedom, large-scale structural analyses are performed through the PEGASUS supercomputer, which is installed in our laboratory. In the first stage, the curved shape of the actuator and the internal stress in each layer are obtained by the cured curvature analysis. Subsequently, the displacement due to the piezoelectric force (which is resulted from applied voltage) is also calculated. The performance of composite curved actuator is investigated by comparing the displacements obtained by the variation of thickness and elastic modulus of laminated composite layers. In order to consider the finite deformation in the first analysis stage and include the pre-stress due to curing process in the second stage, nonlinear finite element analyses are carried out.

• Transactions on Electrical and Electronic Materials
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• 제6권4호
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• pp.135-139
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• 2005

In this paper, negative SU-8 photoresist processed at low temperature is characterized in terms of delamination. Based on a $3^3$ factorial designed experiment, 27 samples are fabricated, and the degree of delamination is measured for each. In addition, nine samples are fabricated for the purpose of verification. Employing the. neural network modeling technique, a process model is established, and response surfaces are generated to investigate degree of delamination associated with three process parameters: post exposure bake (PEB) temperature, PEB time, and exposure energy. From the response surfaces generated, two significant parameters associated with delamination are identified, and their effects on delamination are analyzed. Higher PEB temperature at a fixed PEB time results in a greater degree of delamination. In addition, a higher dose of exposure energy lowers the temperature at which the delamination begins and also results in a larger degree of delamination. These results identify acceptable ranges of the three process variables to avoid delamination of SU-8 film, which in turn might lead to potential defects in MEMS device fabrication.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권3호
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• pp.128-132
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• 2004

The perovskite ferroelectric materials of the PZT, SBT and BST series will attract much attention for application to ULSI devices. Among these materials, the BST ($Ba_0.6$$Sr_0.4$/$TiO_3$) is widely considered the most promising for use as an insulator in the capacitors of DRAMS beyond 1 Gbit and high density FRAMS. Especially, BST thin films have a good thermal-chemical stability, insulating effect and variety of Phases. However, BST thin films have problems of the aging effect and mismatch between the BST thin film and electrode. Also, due to the high defect density and surface roughness at grain boundarys and in the grains, which degrades the device performances. In order to overcome these weakness, we first applied the chemical mechanical polishing (CMP) process to the polishing of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. BST ferroelectric film was fabricated by the sol-gel method. And then, we compared the surface characteristics before and after CMP process of BST films. We expect that our results will be useful promise of global planarization for FRAM application in the near future.

• 대한전자공학회논문지
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• 제26권11호
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• pp.1672-1678
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• 1989

Major problems preventing the device-quality GaAs/Si heterostructure are the lattice mismatch of about 4% and difference in thermal expansion coefficient by a factor of 2.64 between Si and GaAs. Ge is a good candidate for the buffer layer because its lattice parameter and thermal expansion coefficient are almost the same as those of GaAs. As a first step toward developing heterostructure such as GaAs/Ge/Si entirely by a home-built PAE (plasma-assisted epitaxy), Ge films have been deposited on p-type Si (100)substrate by the plasma assisted evaporation of solid Ge source. The characteristics of these Ge/Si heterostructure were determined by X-ray diffraction, SEM and Auge electron spectroscope. PAE system has been successfully applied to quality-good Ge layer on Si substrate at relatively low temperature. Furthermore, this system can remove the native oxide(SiO2) on Si substrate with in-situ cleaning procedure. Ge layer grown on Si substrate by PAE at substrate temperature of 450\ulcorner in hydrogen partial pressure of 10mTorr was expected with a good buffer layer for GaAs/Ge/Si heterostructure.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.1638-1641
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• 2008

We have investigated the effectiveness of a gravure printing method for the fabrication of organic light-emitting diode (OLED) and Organic Thin Film Transistor (OTFT). Printing of the organic layers was performed with a small-scale gravure coating machine, while the metallic layers were vacuum-evaporated. Devices with gravure-printed layers are at least comparable with the spin-coated devices. Effects of the solvent formulation and surface energy mismatch between the organic layer materials on the printed patterns and device performance were discussed. We will present the initial design and experimental data of OTFT fabricated by roll-type soft contact transfer process.