• 제목/요약/키워드: device fabrication

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A Study on the Improvement of Forward Blocking Characteristics in the Static Induction Transistor (Static Induction Transistor의 순방향 블로킹 특성 개선에 관한 연구)

  • Kim, Je-Yoon;Jung, Min-Chul;Yoon, Jee-Young;Kim, Sang-Sik;Sung, Man-Young;Kang, Ey-Goo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07a
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    • pp.292-295
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    • 2004

  • The SIT was introduced by Nishizawa. in 1972. When compared with high-voltage, power bipolar junction transistors, SITs have several advantages as power switching devices. They have a higher input impedance than do bipolar transistors and a negative temperature coefficient for the drain current that prevents thermal runaway, thus allowing the coupling of many devices in parallel to increase the current handling capability. Furthermore, the SIT is majority carrier device with a higher inherent switching speed because of the absence of minority carrier recombination, which limits the speed of bipolar transistors. This also eliminates the stringent lifetime control requirements that are essential during the fabrication of high-speed bipolar transistors. This results in a much larger safe operating area(SOA) in comparison to bipolar transistors. In this paper, vertical SIT structures are proposed to improve their electrical characteristics including the blocking voltage. Besides, the two dimensional numerical simulations were carried out using ISE-TCAD to verify the validity of the device and examine the electrical characteristics. A trench gate region oxide power SIT device is proposed to improve forward blocking characteristics. The proposed devices have superior electrical characteristics when compared to conventional device. Consequently, the fabrication of trench oxide power SIT with superior stability and electrical characteristics is simplified.

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Electric properties of DLC Emitter (DLC Emitter 전기적 특성)

  • Lee, Sang-Heon
    • Proceedings of the KIEE Conference
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    • 2009.07a
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    • pp.1312_1313
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    • 2009

  • In this study the fabrication technique of the planner field emission device structure with a DLC layer were studied. The bottom Mo electrode using electrochemical method on the DLC layer deposited using assist sputtering.

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