• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.803-806
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• 2007

Since the different characteristics from the PRNG (Pseudo Random Number Generator) or various deterministic devices such as arithmetic processing units, new concepts and test methods should be suggested in order to test TRNG (Ture Random Number Generator). Deterministic devices can be covered by ATPG (Automatic Test Pattern Generation), which uses patterns generated by cyclic shift registers due to its hardware oriented characteristics, pure random numbers are not possibly tested by automatic test pattern generation due to its analog-oriented characteristics. In this paper, we studied and analyzed a hardware/software combined test method named Diehard test, in which we apply continuous pattern variation to check the statistics. We also point out the considerations when making random number tests.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.610-618
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• 2003

Recently, many deterministic built-in self-test schemes to reduce test time have been researched. These schemes can achieve a good quality test by shortening the whole test process, but require complex algorithms or much hardware. In this paper, a new deterministic BIST scheme is provided that reduces the additional hardware requirements, as well as keeping test time to a minimum. The proposed BIST (Built-In Self-Test) methodology brings about the reduction of the hardware requirements for pseudo-random tests as well. Theoretical study demonstrates the possibility of reducing the hardware requirements for both pseudo-random and deterministic tests, with some explanations and examples. Experimental results show that in the proposed test scheme the hardware requirements for the pseudo-random test and deterministic test are less than in previous research.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1065-1068
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• 1998

This paper proposes a new test generation method. Most of the test generation methods are gate-level based, but our scheme is VHDL based, especially in other word, behavioral-level based. Our test pattern generation method uses software test method. And we generate deterministic test pattern with this method. The purpose of our method is to reduce the time and effort to generate the test patterns for the end-product test of IC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.81-90
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• 2004

This paper presents new testability measure based on learning, which can be useful in the deterministic process of test pattern generation algorithms. This testability measure uses the structural information that are obtained by teaming. The proposed testability measure searches for test pattern that can early detect the conflict in case of the hardest decision problems. On the other hand in case of the easiest decision problem, it searches for test pattern that likely results in the least conflict. The proposed testability measure reduces CPU time to generate test pattern that accomplishes the same fault coverage as that of the distance-based measure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.81-88
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• 2002

A new pattern generator of BIST based on the pattern clustering is developed. The proposed technique embeds a pre-computed deterministic test set with low hardware overhead for test-per-clock environments. The test control logic is simple and can be synthesized automatically. Experimental results for the ISCAS benchmark circuits show that the effectiveness of the new pattern generator compared to the previous methods.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.6
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• pp.63-70
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• 1994

In this paper, we propose a fault simulation method based on primary output in combinational circuit. In the deterministic test pattern generation, each test pattern is genterated incrementally. The test pattern is applied to the primary inputs of circuit under test to simulate faults. We detect the faults with respect to each primary output. The fault detection with resptect to each primary output is reflected by the corresponding bit in the detection words, and efficient fault detection for the reconvergent fan-out stem is achieved with dynamic fault propagation. As an experimental result of the fault simulation with our method for the several bench mark circuits, we illustrated the good performance showing that the number of gates to be activated is much reduced as compared with other method which is not based on primary output.

• Journal of Advanced Marine Engineering and Technology
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• v.22 no.5
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• pp.687-692
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• 1998

Test pattern generation is one of most difficult problems encountered in automating the design of logic circuits. The goal is to obtain the highest fault coverage with the minimum number of test patterns for a given circuit and fault set. although there have been many deterministic algorithms and heuristics the problem is still highly complex and time-consuming. Therefore new approach-es are needed to augment the existing techniques. This paper considers the problem of test pattern improvement for combinational circuits as a restricted subproblem of the test pattern generation. The problem is to maximize the fault coverage with a fixed number of test patterns for a given cir-cuit and fault set. We propose a new approach by use of a genetic algorithm. In this approach the genetic algorithm evolves test patterns to improve their fault coverage. A fault simulation is used to compute the fault coverage of the test patterns Experimental results show that the genetic algorithm based approach can achieve higher fault coverages than traditional techniques for most combinational circuits. Another advantage of the approach is that the genetic algorithm needs no detailed knowledge of faulty circuits under test.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.526-531
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• 2003

Recently, many BIST(Built-in Self Test) schemes have been researched to reduce test time and hardware. But, most BIST schemes about pattern generation are for deterministic pattern generation. In this paper a new pseudo-random BIST scheme is provided to reduce the existing test hardware and keep a reasonable length of test time. Theoretical study demonstrates the possibility of the reduction of the hardware for pseudo-random test with some explanations and examples. Also the experimental results show that in the proposed test scheme the hardware for the pseudo-random test is much less than in the previous scheme and provide comparison of test time between the proposed scheme and the current one.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.72-84
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• 2000

The test patterns for path delay faults consist of two patterns. So in order to test the delay faults, a new weight generation algorithm that is different from the weight generation algorithm for stuck-at faults must be applied. When deterministic test patterns for weight calculation are used, the deterministic test patterns must be divided into several subsets, so that Hamming distances between patterns are not too long. But this method makes the number of weight sets too large in delay testing, and may generate inaccurate weights. In this pater, we perform fault simulation without pattern partition. Experimental results for ISCAS 89 benchmark circuits prove the effectiveness of the new weight generation algorithm proposed in this paper.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.935-938
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• 1999

메모리 테스트는 Built-In Self Test(BIST)와 같이 메모리에 내장된 회로를 통하여 자체 점검하는 방법과 테스터를 통하여 생성된 패턴을 주입하는 방법이 있다. 테스트 패턴 생성방법으로는 각각의 고장모델에 대한 테스트 패턴을 deterministic하게 생성해주는 방법과 Pseudo Random Pattern Generator(PRPG)를 이용하여 생성하는 경우로 구분할 수 있다. 본 연구에서는 PRPG를 패턴 생성기로 사용하여 여러 가지 메모리의 결함을 대표한다고 볼 수 있는 Static 및 Dynamic Neighborhood Pattern Sensitive Fault(NPSF) 등 다양한 종류의 고장을 점검할 수 있도록 메모리 BIST를 구성하였다. 기존의 Linear Feedback Shift Register(LFSR)보다 본 연구에서 제안하는 Linear Hybrid Cellular Automata(LHCA)를 이용한 PRPG가 높고 안정된 고장 점검도를 나타내었다.