• 제목/요약/키워드: design speed decision

검색결과 134건 처리시간 0.024초

기본설계 단계에서 분산형 고속철도차량의 현가요소 최적화 (Optimization of the Suspension Characteristics for a High Speed Electrical Multiple Train on the Stage of Basic Design)

  • 박찬경;목진용;김기환
    • 한국철도학회:학술대회논문집
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    • 한국철도학회 2009년도 춘계학술대회 논문집 특별세미나,특별/일반세션
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    • pp.183-188
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    • 2009
  • The High speed electrical multiple train having a distributed electrical motor system has just been developing to aim the experimental maximum speed at 400km/h since August, 2007. This project comes in stage of basic design and so, it needs to take some review and analysis the characteristics of suspensions on the view of basic design. The vehicle model for dynamic analysis is made from the concept design model that used for the preliminary design review with Vampire program and it is modeled with three linear secondary dampers and two shear springs separated from the bush elements in previous model. The optimization technique is applied to search the proper range of linear characteristics for the suspension elements to satisfy the stability performance at speed 130m/s (about 460km/h). The results shows there are some optimum points according to the variation of primary and secondary suspension characteristics and it would be useful to make a decision to select the proper suspension elements in the precision design that will be done by the manufacturing company.

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DCS 1800 시스템에서 연판정 출력 등화기에 대한 비터비 복호기 설계 및 구현 (Design and implementation of a viterbi decoder for a soft output equalizer in the DSC 1800 radio system)

  • 김주응;윤석현;이재혁;강창언
    • 전자공학회논문지S
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    • 제35S권3호
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    • pp.19-28
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    • 1998
  • This paper is concerned with the implementation of the equalization technique in a DCS 1800 system employing the soft-decision output Viterbi algorithm (SOVA), which makes the hardware complexity comparable to the hard decision MLSE and gives reliable performance. Also, the channel estimation technique with enhances the perfdormance of the soft-decision output equalizer is proposed, and the Viterbi decoder which operates effectively with the soft-decision output of the qualizer is implemented using the Very High Speed ICs Hardware Description Language (VHDL). From the simulation results, it is shown that the implemented Viterbi decoder operates effectively and the SOVA outperforms the hard-decision MLSE in terms of the frame erasure rate (FER) and bit error rate (BER).

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Low-Complexity Non-Iterative Soft-Decision BCH Decoder Architecture for WBAN Applications

  • Jung, Boseok;Kim, Taesung;Lee, Hanho
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제16권4호
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    • pp.488-496
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    • 2016
  • This paper presents a low-complexity non-iterative soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and design technique for wireless body area networks (WBANs). A SD-BCH decoder with test syndrome computation, a syndrome calculator, Chien search and metric check, and error location decision is proposed. The proposed SD-BCH decoder not only uses test syndromes, but also does not have an iteration process. The proposed SD-BCH decoder provides a 0.75~1 dB coding gain compared to a hard-decision BCH (HD-BCH) decoder, and almost similar coding gain compared to a conventional SD-BCH decoder. The proposed SD-BCH (63, 51) decoder was designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed non-iterative SD-BCH decoder using a serial structure can lead to a 75% reduction in hardware complexity and a clock speed 3.8 times faster than a conventional SD-BCH decoder.

한국형 고속전철 차량시스템의 개념설계 (The Conceptual Design of Korea High Speed Train System)

  • 김경택;정경렬
    • 한국철도학회:학술대회논문집
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    • 한국철도학회 1999년도 추계학술대회 논문집
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    • pp.172-180
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    • 1999
  • The major subject of this paper is to develop the concept fur a Korea high speed train system and recommend to train configuration. High speed train configurations are basically concerned traction power(train configurations with concentrated; CPT or distributed Power system: DPT) and train design(single car as compared with articulated bogies). The result of configuration, a advantages and disadvantaged were necessitated by different train configurations; -distributed underfloor power have an increased length for the seats by 15% as compared with the concentrated power trait - articulated trainsets are characterised by less of number of bogies and reduced values of mass, train resistance, noise and vibration. from the result, the optimized train concept combining high seat capacity per train length with low weight and train resistance is 400m long, single -floor train composed of two symmetrically arranged half trainsets. Therefore, at this work recommended distributed train system However, the final decision of Korea high speed train configuration was concentrated power train and articulated bogie system. The configuration of trainset was 20cars included 2 power cars, 4 motorized cars and 14 trailer cars.

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교량-궤도 종방향 상호작용 및 동적영향을 고려한 고속철도 교량의 최적설계 (Optimum Design of High-Speed Railway Bridges Considering Bridge-Rail Longitudinal Interaction and Moving Load Effect)

  • 임영록;임석빈;박광영
    • 한국방재학회 논문집
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    • 제10권6호
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    • pp.27-34
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    • 2010
  • 최근 친환경 운송수단인 고속철도에 대한 관심이 증가하고 있으며, 그에 따른 고속철도 교량이 많이 건설되고 있다. 하지만 기존의 일반 철도 교량에 비해 고속철도 교량은 고속주행하는 열차의 동적 하중에 의한 영향이 증가하게 되므로, 이에 대한 고려가 필요한 실정이다. 따라서 본 연구에서는 고속주행하는 열차의 주행 안정성을 확보하기 위해 고속철도 교량의 구조물-궤도 상호작용 및 동적 안전성을 동시에 고려하여 설계하는 방법을 제안하였고, 제안한 알고리즘의 효율성을 입증하기 위하여 기존의 재래식 설계에 의하여 설계, 시공되어진 단순 5경간 250 m 교량을 대상으로 수치해석을 수행하여 비교하였다. 수치해석 결과, 교량-궤도 상호작용 및 교량-차량 상호작용을 동시에 고려한 최적설계가 기존의 제안된 여러 설계 방법들과 비교했을 때, 최적화의 목적함수로 설정한 생애주기비용이 가장 경제적임을 확인하였다.

콘크리트궤도에 고속분기기 설치를 고려한 교량설계 및 시공기법 (Design and Construction Method Considering Turnout for High-speed on The Bridge with Concrete Track)

  • 김인재;오세영;주환중
    • 한국철도학회:학술대회논문집
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    • 한국철도학회 2008년도 춘계학술대회 논문집
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    • pp.71-79
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    • 2008
  • The concrete track is being used at the Phase II of the Kyeongbu High Speed Railway and New Constructed Honam High Speed Railway. When it makes a decision of bridge type, It has to consider about longitudinal forces of Continuous Welded Rail, Displacement at the end of bridges, Up-lift forces for fastener on the track. If it is installed turnout on the bridge, There is likelihood of the deck twist by applying the each difference longitudinal forces at the 4 each rails and the buckling by concentration of rail stress at the turnout. Moreover, If it is installed turnout on the continuous bridge and REJ(Rail Expansion Joint) on the main track or turnout track. It is hard to keep a safety for rail because of coming to twist or folding at the expansion of deck on the turnout track. Therefore when it is a design of bridge with turnout. It need to take bridge type to minimize an additional axial force and a displacement at the turnout. This paper makes a study of the composite steel arch bridge that is able to resolve criteria requirements of safety for track with turnout and suggest a helpful design method for bridge considering track with turnout by being based on design and construction method of Eonyang Bridge at the north part of Ulsan Station in Phase II of the Kyeongbu High Speed Railway.

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Redundant Binary 복소수 필터를 이용한 적응 결정귀환 등화기 모듈 설계 (A design of Adaptive Decision-feedback Equalizer Module using Redundant Binary Complex Filter)

  • 김호하;안병규신경욱
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1998년도 추계종합학술대회 논문집
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    • pp.1125-1128
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    • 1998
  • A new architecture for high-speed implementation of adaptive decision-feedback equalizer (ADFE) applicable to wide-band digital wireless modems is described. Rather than using conventional two's complement arithmetic, a novel complex-valued filter structure is devised, which is based on redundant binary (RB) arithmetic. The proposed RB complex-valued filter reduces the critical path delay of ADFE, as well as leads to a more compact implementation than conventional methods. Also, the carry-propagation free (CPF) operation of the RB arithmetic enhances its speed. To demonstrate the proposed method, a prototype chip set is designed. They are designed to contain two complexvalued filter taps along with their coefficient updating circuits, and can be cascaded to implement loger filter taps for high bit-rate applications.

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DWW 알고리즘을 적용한 고속 가중 FDNN의 설계 (Design of high speed weighted FDNN applied DWW algorithm)

  • 이철희;변오성;문성룡
    • 전자공학회논문지C
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    • 제35C권7호
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    • pp.101-108
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    • 1998
  • In this paper, after we got to realized FDNN (fuzzy decision neural network) applied the quantization triangularity fuzzy function to DBNN(decision based neural network) of a hierarchical structure for image process, we could esign hardware of the realized FDNN. Also it is normalized the standard image and the input image as the same size. We are applied DWW algorithm which selected the closest value with finding similarity of an interval image by this distance to FDNN. So we could calulated in terms of distance to weight of pixel which composed two image and eliminated the nise of image, minimized the lost of information, obtained the optimal information. It is designed hardware of high speed weighted FDNN using COMPASS tool. Aslo, the total circuit is realized as gates of 61,000 and could show to superiority of FDNN using the simulation.

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Highway traffic noise modeling and estimation based on vehicles volume and speed

  • Rassafi, Amir Abbas;Ghassempour, Jafar
    • Advances in environmental research
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    • 제4권4호
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    • pp.211-218
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    • 2015
  • Traffic noise estimation models are useful in evaluation of the noise pollution in current circumstances. They are helpful tools for design and planning new roads and highways. Measurement of average traffic noise level is possible when traffic speed and volume are known. The objective of this study was to devise a model for prediction of highway traffic noise levels based on current traffic variables in Iran. The design of this model was to take the impact of traffic congestion into consideration and to be field tested. This study is a library research augmented by field study conducted on Saeedi Highway located south west of Tehran. The period for the field study lasted 5 days from 7-12 February, 2013. This study examined liner and non-liner methods in formulation of its model. Liner method without a fixed coefficient was the best fit for the intended model. The proposed model can serve as a decision making tool to estimate the impact of key influential factors on sound pressure levels in urban areas in Iran.

A Bit-level ACSU of High Speed Viterbi Decoder

  • Kim, Min-Woo;Cho, Jun-Dong
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제6권4호
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    • pp.240-245
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    • 2006
  • Viterbi decoder is composed of BMU(Branch metric Unit), ACSU(Add Compare Select Unit), and SMU(Survivor path Memory Unit). For high speed viterbi decoders, ACSU is the main bottleneck due to the compare-select and feedback operation. Thus, many studies have been advanced to solve the problem. For example, M-step look ahead technique and Minimized method are typical high speed algorithms. In this paper, we designed a bit-level ACSU(K=3, R=1/2, 4bit soft decision) based on those algorithms and switched the matrix product order in the backward direction of Minimized method so as to apply Code-Optimized-Array in order to reduce the area complexity. For experimentation, we synthesized our design by using SYNOPSYS Design compiler, with TSMC 0.18 um library, and verified the timing by using CADENCE verilog-XL.