• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.11
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• pp.1-8
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• 2011

In this paper, we study receiver design issue to apply the OFDM based WLAN specification, such as 802.11p, to the communications in high speed mobile environment, e.g., for the ICT based railroad control on a train having its speed up to 300 km/hr. To successfully apply the existing WLAN specifications without modifying its transmission format, the performance at the receiver will solely depends on the channel estimation performance if we ignore the affect of frequency offset With a speed of multiple hundred km/hr, the channel estimation using only the preamble will not provide enough precision since the channel changes so fast. Therefore, in this paper, taking the high mobility into account, we focus on the design of decision directed channel estimation and equalization techniques and perform simulations to evaluate and compare their performances and to finally confirm the applicability of the existing WLAN specification to the systems with very high mobility.

• Journal of Drive and Control
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• v.18 no.2
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• pp.20-31
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• 2021

An excavator is a construction machine that can perform various tasks such as trenching, piping, excavating, slope cutting, grading, and rock demolishing. In the 2010s, unmanned construction equipment using ICT technology was continuously developed. In this paper, the path design process was studied to implement the output data of the decision stage, and the path design algorithm was developed. For example, the output data of the decision stage were terrain data around the excavator, excavator mechanism information, excavator hydraulic information, the position and posture of the bucket at key points, the speed of the desired bucket path, and the required excavation volume. The result of the path design was the movement of the hydraulic cylinder, boom arm, bucket, and bucket edge. The core functions of the path design algorithm are the function of avoiding impact during the excavation process, the function to calculate the excavation depth that satisfies the required excavation volume, and the function that allows the bucket to pass through the main points of the excavation process while maintaining the speed of the desired path. In particular, in the process of developing the last function, the node tracking method expressed in the path design table was newly developed. The path design algorithm was verified as this path design satisfied the JCMAS H02 requirement.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.2
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• pp.8-18
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• 1993

A multi-font, multi-size and high speed character recognition system is designed. The design principles are simpilcity of algorithm, adaptibility, learnability, hierachical data processing and attention by feed back. For the multi-size character recognition, the extracted character images are normalized. A hierachical classifier classifies the feature vectors. Feature is extracted by applying the directional receptive field after the directional dege filter processing. The hierachical classifier is consist of two pre-classifiers and one decision making classifier. The effect of two pre-classifiers is prediction to the final decision making classifier. With the pre-classifiers, the time to compute the distance of the final classifier is reduced. Recognition rate is 95% for the three documents printed in three kinds of fonts, total 1,700 characters. For high speed implemention, a multiprocessor system with the ring structure of four transputers is implemented, and the recognition speed of 30 characters per second is aquired.

• The Research Journal of the Costume Culture
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• v.21 no.1
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• pp.117-128
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• 2013

Studies show that time pressure affects the purchase decision-making process of consumers. However, in the case of apparel shopping, few studies have looked into the influence of time pressure on the purchase decision-making process. This study aims to determine how perceived time pressure in apparel shopping, time pressure situations, and product type and the interactions between these variables influence the clothing purchase process. An empirical study was conducted among males and females in their 20s and 30s. Perceived time pressure in apparel shopping was measured using four items. Time pressure situations and product types were given in the form of scenarios. A $2{\times}2{\times}2$ experimental design was used, and perceived time pressure in apparel shopping, time pressure situations, and product type were used to create eight different situations. The dependent variables included decision-making speed, anticipated regret, and anticipated purchase satisfaction. Data from 512 subjects were collected through an online data collection. Results showed that the high perceived time pressure group and the shopping situation with time pressure involved a significantly high level of decision-making time, anticipated regret, and anticipated purchase satisfaction. Marketers must understand the real-time pressure situations of consumers.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.12
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• pp.1248-1255
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• 2003

High-speed QPSK demodulator has been one important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes Zero-Crossing IF-level(ZCIF) QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. ZCIF QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tracking to fabricate FPGA chip. The testing results of the implemented onto CPLD-FLEX10K chip show demodulation speed is reached up to 2.6［Mbps］. Actually in case of designing by ASIC, its speed may be faster than CPLD by 5 times. Therefore, it is possible to fabricate the ZCIF QPSK demodulator with speed of 10 Mbps.

• Journal of Korean Tunnelling and Underground Space Association
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• v.14 no.4
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• pp.375-395
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• 2012

According to the local highway tunnel ventilation guideline, ventilation capacity calculation should be performed at the speed ranging from 10 km/h to 80 km/h. This is so reasonable method considering uncongested and congested traffic conditions in urban tunnels. But recently due to low traffic volume and very low congestion frequency in rural highway tunnels, it seems to be an inadequate way to apply the guideline. Therefore the calculation should be performed separately for the free flow and congested traffic cases classified by the appropriate decision model. This paper aims at determining unnecessary running speed range for reasonable tunnel ventilation design, considering free flow and congested traffic conditions. Firstly, traffic volumes in highway tunnels were collected and if any, the causes of congestion were investigated. And with concept of 'margin speed'($u-u_m$), the decision model on traffic congestion was developed. Applicability of the decision model was also analyzed with case study. According to the results, when design speed is 100 km/h, with V/C less than 0.1, then the range of unnecessary speed in tunnel ventilation design is less than 40 km/h; for $V/C{\leqq}0.35$, $V/C{\leqq}0.6$ and $V/C{\leqq}0.75$, the unnecessary speed ranges are found to be ${\leqq}30$, ${\leqq}20$ and ${\leqq}10km/h$, respectively.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.238-241
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• 2000

This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA. (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL models. We have peformed logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5 $\mu\textrm{m}$ standard cell library (STD80). The total number of gates is about 130,000.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.11
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• pp.1171-1177
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• 2009

A missile warning radar is an essential sensor for active protection system to detect antitank missile in all weather environments. This paper introduces missile warning radar for main battle tank and presents the results of the design and implementation of the radar signal processor using high speed multi-DSP. The key algorithms include adaptive CF AR, weighted linear fitting algorithm, S/W tracking capability, and threat decision and present test result.

• Wind and Structures
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• v.14 no.1
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• pp.71-80
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• 2011

This study presents a decision making process for installation of wind barrier which is used to reduce the wind speed applied to running vehicles on expressway. To determine whether it is needed to install wind barrier or not, cost and benefit from wind barrier are calculated during lifetime. In obtaining car accidental risk, probabilistic distribution of wind speed, daily traffic volume, mixture ratio in the volume, and duration time for wind speed range are considered. It is recommended to install wind barrier if benefit from the barrier installation exceed construction cost. In the numerical examples, case studies were shown for risk and benefit calculation and main risky regions on Korean highway were all evaluated to identify the number of installation sites.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.90-97
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• 2006

In this paper, we present a cost-effective architecture of high-speed soft-decision Viterbi decoder for Multi-band OFDM(MB-OFDM) systems. In the design of modem for MB-OFDM systems, a parallel processing architecture is general]y used for the reliable hardware implementation, because the systems should support a very high-speed data rate of at most 480Mbps. A Viterbi decoder also should be designed by using a parallel processing structure and support a very high-speed data rate. Therefore, we present a optimized hardware architecture for 4-way parallel processing Viterbi decoder in this paper. In order to optimize the hardware of Viterbi decoder, we compare and analyze various ACS architectures and find the optimal one among them with respect to hardware complexity and operating frequency The Viterbi decoder with a optimal hardware architecture is designed and verified by using Verilog HDL, and synthesized into gate-level circuits with TSMC 0.13um library. In the synthesis results, we find that the Viterbi decoder contains about 280K gates and works properly at the speed required in MB-OFDM systems.