• International Journal of Highway Engineering
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• v.14 no.4
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• pp.103-111
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• 2012

PURPOSES : Effective speed management is necessary for preventing traffic crashes on the road. Speed hump is known as an effective tool for managing speed. Unlike existing studies which are mainly focused on humps for vehicles, this study proposed a novel method to determine design parameters for bicycle speed humps based on a multi-criteria decision making process. METHODS : Three objectives including the effectiveness of speed reduction, bicycle safety, and user's comfortability were incorporated into the proposed evaluation framework for determining design parameters. A multi-criteria value function was also derived and utilized as a part of the proposed method. RESULTS : Extensive simulations and statistical tests show that an integrated bike-box way is identified as the best in terms of operational efficiency and safety. CONCLUSIONS : It is expected that the outcomes of this study can be a valuable precursor for developing design guidelines for bicycle road and facility.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.74-86
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• 2002

This paper proposes a VLSI architecture for high-speed data processing of the differential phase detectors with the decision feedback. To improve the BER performance of the conventional differential phase detection, DF-DPD, DPD-RGPR and DFDPD-SA have been proposed. These detection methods have the architecture feedbacking the detected phase to reduce the noise of the previous symbol as phase reference. However, the feedback of the detected phase results in lower data processing speed than that of the conventional differential phase detection. In this paper, the VLSI architecture was proposed for high-speed data processing of the differential phase detectors with decision feedback. The Proposed architecture has the pre-calculation method to previously calculate the results on 'N'th step at 'M-1'th step and the pre-decision feedback method to previously feedback the predicted phases at 'M-1'th step. The architecture proposed in this paper was implemented to RTL using VHDL. The simulation results show that the Proposed architecture obtains the high-speed data processing.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.24 no.5
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• pp.425-431
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• 2006

Recently, the government has adjusted the 4th National Master Plan in an effect to achieve balanced national land development. However, the current traffic accident index ranks among the lowest in OECD countries, ranking 25th out of 29 countries. Therefore, this study is aimed at indicating problems with National Expressway and local roads developing a solution by analyzing the problems and suggesting the most appropriate design speed for inter-changes where the traffic accidents occur frequently. With the results, it is to obtain a design speed decision formula at interchange branch points to prevent traffic accidents, secure safe and optimal road conditions and maximize traffic load capability.

• Journal of the Korean Society for Railway
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• v.7 no.2
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• pp.107-113
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• 2004

This study presents a development of DeCatS(Detail Design of High Speed Catenary System) which is a software to design high speed catenary system automatically. The program is developed by Korea Railroad Research Institute with the support of KHSR. A process of developing it and a comparison with LEXCAT. in order to demonstrate a preciseness of that, were performed. In the program, decision of H-beam, cantilever fitting, management of materials, automatic drawing and etc. according to input conditions can be accomplished. In this study, especially the program algorithm for the decision of mast was introduced.

• Proceedings of the KSR Conference
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• 2011.05a
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• pp.644-651
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• 2011

This study presents a development of DeCatS(Detail Design of High Speed Catenary System) which is a software to design high speed catenary system automatically. The program is developed by Korea Railroad Research Institute with the support of KHSR. A process of developing it and a comparison with LEXCAT, in order to demonstrate a preciseness of that, were performed. In the program, decision of H-beam, cantilever fitting, management of materials, automatic drawing and etc. according to input conditions can be accomplished. In this study, especially the program algorithm for the decision of mast was introduced.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.1195-1200
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• 2008

The railway bridge design specification used in our country at present, is reflected results that take into account link between vehicle and roadbed according to decision of TGV vehicle style in 1994, and executes design verification. Hereafter, the particular loading condition and the design speed of the high-speed EMU that is recognized to the next generation of high speed railway, are plain difference with TGV vehicle style decided in 1994. The effect that these load and design speed get in roadbed, especially superstructure, displays difference with the existent high speed railway. The goal of this study is to choose the suitable bridge type, and to reduce the construction cost for the next generation of railway, i.e., the high-speed EMU.

• Journal of the Korean Society for Railway
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• v.12 no.3
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• pp.427-436
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• 2009

This paper introduced Railway Network Design Problem (RNDP) to provide priority decisions on high-speed railway investment scenarios defined by various network segments and train systems. The RNDP optimizes the objective functions of minimize total travel time. Results show that the priority of high-speed railway investment is found to be East-west, West-coast, and South-coast line respectively. An entirely new line built with 400km/h is found to be the best alternative to East-west line. Regarding West-coast and South-coast line, the combined alternative of upgrading Geolla and Kyeonjon line with 200km/h and building a new line with 400km/h and 350km/h for remains of each line is the best.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.226-230
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• 2000

In this paper, we implemented the QPSK demodulator with a CPLD chip, and examined the results. DD(Decision Directed)-Gardner algorithm is used for STR loop and Decision-Directed algorithm is used for CPR loop. The speed of the QPSK demodulator implemented in FLEX10K chip can be guaranteed approximately 2[Mbpsl] transmission speed. In practical designed by ASIC, the speed is faster than that of CPLD by 5-6 times.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.31 no.1D
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• pp.65-72
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• 2011

When an expressway intersects another expressway, a unique connector needs to be designed between the two consecutive exit ramps. In such a case, it is important to design a connector such that there is enough distance for drivers to find their way safely. A current design manual in Korea prescribes the minimum length of the connector as 240 m. In this research, we have suggested a method for calculating the minimum length of a connector in order to check the feasibility of the currently prescribed length. For this purpose, we have attempted to determine the total perception-reaction time and lane-changing time required by a driver. For determining the driver's perception-reaction time, we have used the driver's decision time in addition to the conventional 2.5 s of perception-reaction time for stopping sight distances. We have considered both the design speed and the average travel speed for the calculation of the length. To evaluate the accuracy of the new method, we have chosen four sites on expressways for which relatively high accident rates were recorded. As a result, we could verify that the current limit (240 m) was sufficient for drivers to be able to change lanes in the given specific geometry. However, the prescribed limit should be revised in case the drivers' decision time is considered to be their perception-reaction time. All new approaches for calculating the ideal length of a connector have been carried out by taking into account the design speed as well as the average travel speed. Owing to the characteristics of the specific geometry for two consecutive exit ramps and the large difference between the design speed and the average travel speed in the objective areas, it is more realistic to use the proposed method by keeping the decision time equal to a driver's perception-reaction time, in order to determine the ideal distance that should be maintained between two consecutive exit ramps.

• Journal of Korea Society of Industrial Information Systems
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• v.8 no.1
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• pp.83-91
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• 2003

High-speed QPSK demodulator has been in important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes all-digital QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. All-digital QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tacking to fabricate FPGA chip. The testing results of the implemented onto CPLD-EPF10K100GC 503-4 chip show demodulation speed is reached up to 2.6[Mbps]. If it is implemented a CPLD chip with speed grade 1, the demodulation speed can be faster by about 5 times. Actually in case of designing by ASIC, its speed my be faster than CPLD by 5 times. Therefore, it is possible to fabricate the all-digital QPSK demodulator chipset with speed of 50[Mbps].