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Numerical Simulation of Crash Impact Test for Fuel Tank of Rotorcraft (회전익항공기용 연료탱크 충돌충격시험 수치모사 연구)

  • Kim, Hyun-Gi;Kim, Sung-Chan;Lee, Jong-Won;Hwang, In-Hee;Kim, Kyung-Soo
    • Journal of the Computational Structural Engineering Institute of Korea
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    • v.24 no.5
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    • pp.521-530
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    • 2011
  • Since aircraft fuel tanks have many interfaces connected to the airframe as well as the fuel system, they have been considered as one of the system-dependent critical components. Crashworthy fuel tanks have been widely implemented to rotorcraft and rendered a great contribution for improving the survivability of crews and passengers. Since the embryonic stage of military rotorcraft history began, the US army has developed and practised a detailed military specification documenting the unique crashworthiness requirements for rotorcraft fuel tanks to prevent most, hopefully all, fatality due to post-crash fire. The mandatory crash impact test required by the relevant specification, MIL-DTL-27422D, has been recognized as a non-trivial mission and caused inevitable delay of a number of noticeable rotorcraft development programs such as that of V-22. The crash impact test itself takes a long-term preparation efforts together with costly fuel tank specimens. Thus a series of numerical simulations of the crash impact test with digital mock-ups is necessary even at the early design stage to minimize the possibility of trial-and-error with full-scale fuel tanks. In the present study the crash impact simulation of a few fuel tank configurations is conducted with the commercial package, Autodyn, and the resulting equivalent stresses and internal pressures are evaluated in detail to suggest a design improvement for the fuel tank configuration.

Design of Digital PLL with Asymmetry Compensator in High Speed DVD Systems (고속 DVD 시스템에서 비대칭 신호 보정기와 결합한 Digital PLL 설계)

  • 김판수;고석준;최형진;이정현
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.12A
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    • pp.2000-2011
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    • 2001
  • In this Paper, we convert conventional low speed(1x, 6x) DVD systems designed by analog PLL(Phase Locked Loop) into digital PLL to operate at high speed systems flexibly, and present optimal DPLL model in high speed(20x) DVD systems. Especially, we focused on the design of DPLL that can overcome channel effects such as bulk delay, sampling clock frequency offset and asymmetry phenomenon in high speed DVD systems. First, the modified Early-Late timing error detector as digital timing recovery scheme is proposed. And the four-sampled compensation algorithm using zero crossing point as asymmetry compensator is designed to achieve high speed operation and strong reliability. We show that the proposed timing recovery algorithm provides enhanced performances in jitter valiance and SNR margin by 4 times and 3dB respectively. Also, the new four-sampled zero crossing asymmetry compensation algorithm provides 34% improvement of jitter performance, 50% reduction of compensation time and 2.0dB gain of SNR compared with other algorithms. Finally, the proposed systems combined with asymmetry compensator and DPLL are shown to provide improved performance of about 0.4dB, 2dB over the existing schemes by BER evaluation.

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Design and Implementation of 8b/10b Encoder/Decoder for Serial ATA (직렬 ATA용 8b/10b 인코더와 디코더 설계 및 구현)

  • Heo Jung-Hwa;Park Nho-Kyung;Park Sang-Bong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.1A
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    • pp.93-98
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    • 2004
  • Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.

A High Speed Block Turbo Code Decoding Algorithm and Hardware Architecture Design (고속 블록 터보 코드 복호 알고리즘 및 하드웨어 구조 설계)

  • 유경철;신형식;정윤호;김근회;김재석
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.7
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    • pp.97-103
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    • 2004
  • In this paper, we propose a high speed block turbo code decoding algorithm and an efficient hardware architecture. The multimedia wireless data communication systems need channel codes which have the high-performance error correcting capabilities. Block turbo codes support variable code rates and packet sizes, and show a high performance due to a soft decision iteration decoding of turbo codes. However, block turbo codes have a long decoding time because of the iteration decoding and a complicated extrinsic information operation. The proposed algorithm using the threshold that represents a channel information reduces the long decoding time. After the threshold is decided by a simulation result, the proposed algorithm eliminates the calculation for the bits which have a good channel information and assigns a high reliability value to the bits. The threshold is decided by the absolute mean and the standard deviation of a LLR(Log Likelihood Ratio) in consideration that the LLR distribution is a gaussian one. Also, the proposed algorithm assigns '1', the highest reliable value, to those bits. The hardware design result using verilog HDL reduces a decoding time about 30% in comparison with conventional algorithm, and includes about 20K logic gate and 32Kbit memory sizes.

Heat Transfer on Supersonic Nozzle using Combined Boundary Layer Integral Method (수치해석 통합기법을 이용한 노즐 내열재 표면의 열전달 해석)

  • Bae, Ji-Yeul;Bae, Hyung Mo;Ryu, Jin;Ham, Heecheol;Cho, Hyung Hee
    • Journal of the Computational Structural Engineering Institute of Korea
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    • v.30 no.1
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    • pp.47-53
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    • 2017
  • A boundary layer integral combined with a 1-D isentropic core flow model has been successfully used to determine heat transfer rate on the surface of a supersonic nozzle. However its accuracy is affected by the core flow condition which is used as a boundary condition for the integral calculation. Because flow behavior near a nozzle throat deviates from 1-D isentropic condition due to 2-D flow turning and interaction between core flow and boundary layer, accuracy of heat transfer calculation decreases at a nozzle throat. Therefore, CFD is adopted to deduce improved core flow condition and increase accuracy of boundary layer integral at nozzle throat in this research. Euler model and SST $k-{\omega}$ model is solved by CFD code and used as a boundary condition for boundary layer integral. Developed code is tested in the supersonic nozzle from the previous research and improvement in accuracy is observed, especially at nozzle throat and diverging section of the nozzle. Error between experimental result and calculation result reduced by 16% when a calculation is made based on the SST $k-{\omega}$ model. Method developed in this research is expected to be used in thermal design of the rocket nozzle.

The Design and Implementation of the Real-time Data Stream Server for Continuity of Care Record (실시간 헬스케어 시스템을 위한 데이터 스트림 서버의 설계 및 구현)

  • Wu, Zejun;Li, Yan;Bae, Hae-Young
    • Journal of the Korea Society of Computer and Information
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    • v.16 no.12
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    • pp.71-81
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    • 2011
  • The EMR management services can monitoring the patients' record with any doctors in any hospital by using the internet and smartphones online. To handle the real time, multidimensional, continuous data, database management systems (DBMS) must cope with high insert rates for updates, however the traditional DBMS suffers from processing these kinds of data due to its serious design bottlenecks. So the researchers put forward to Data Stream Management System (DSMS). In this paper we describe the real-time Data Stream Server for Continuity of Care Record (CCR) that including continuos query processor. This system is compiled with DSMS and DBMS in EMR system for processing and monitoring the coming CCR data stream, and also storing the processed result with high-efficiency. The system enables users not only to query stored CCR information from DBMS, but also to execute continue query on real-time CCR Data Stream, and health information can be transferred between different healthcare providers that would reduce medical error. At last, we develop a IPhone mobile application to test the proposed real-time data stream server.

Evaluation of Shrinkage Strain of Alkali-Activated Slag Concrete (알칼리활성 슬래그 콘크리트의 건조수축 변형률 평가)

  • Yang, Keun-Hyeok;Seo, Eun-A
    • Journal of the Korea Concrete Institute
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    • v.25 no.6
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    • pp.593-599
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    • 2013
  • The unrestrained shrinkage strain of alkali-activated (AA) slag concrete was examined and compared with design equations specified in code provisions and empirical equations proposed by Yang et al. The main parameters investigated were the water-to-binder ratio (W/B), unit water content and fine aggregate-to-total aggregate ratio (S/a). Test results revealed that shrinkage strain of AA slag concrete is nearly proportional to the W/B ratio, whereas its time function is independent of the W/B ratio. The shrinkage strain of AA slag concrete increased significantly when the unit water content is above $185kg/m^3$, whereas it is marginally affected by the S/a ratio. The design equation of ACI 209 considerably overestimates the shrinkage behavior of AA slag concrete, whereas CEB-FIP equation tends to underestimate the shrinkage at the age more than 28 days. The empirical equation of Yang et al. is in better agreement with test results, showing that values of mean and standard deviation of error coefficients obtained from each specimen are 016 and 0.07, respectively.

Fabrication of IMT-2000 Linear Power Amplifier using Current Control Adaptation Method in Signal Cancelling Loop (신호 제거 궤환부의 전류 제어 적응형 알고리즘을 이용한 IMT-2000용 선형화 증폭기 제작)

  • 오인열;이창희;정기혁;조진용;라극한
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.40 no.1
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    • pp.24-36
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    • 2003
  • The digital mobile communication will be developed till getting multimedia service in anyone, any where, any time. Theses requiring items are going to be come true via IMT-2000 system. Transmitting signal bandwidth of IMT-2000 system is 3 times as large as IS-95 system. That is mean peak to average of signal is higher than IS-95A system. So we have to design it carefully not to effect in adjacent channel. HPA(High Power Amplifier) located in the end point of system is operated in 1-㏈ compression point(Pl㏈), then it generates 3rd and 5th inter modulation signals. Theses signals affect at adjacent channel and RF signal is distorted by compressed signal which is operated near by Pl㏈ point. Then the most important design factor is how we make HPA having high linearity. Feedback, Pre-distorter and Feed-forward methods are presented to solve theses problems. Feed-forward of these methods is having excellent improving capacity, but composed with complex structure. Generally, Linearity and Efficiency in power amplifier operate in the contrary, then it is difficult for us to find optimal operating point. In this paper we applied algorithm which searches optimal point of linear characteristics, which is key in Power Amplifier, using minimum current point of error amplifier in 1st loop. And we made 2nd loop compose with new structure. We confirmed fabricated LPA is operated by having high linearity and minimum current condition with ACPR of -26 ㏈m max. @ 30㎑ BW in 3.515㎒ and ACLR of 48 ㏈c max@${\pm}$㎒ from 1W to 40W.

Design and Analysis of 4D-8PSK-TCM System Considering the Nonlinear HPA Environment (비선형 HPA 환경을 고려한 4D-8PSK-TCM 시스템의 설계 및 분석)

  • An, Changyoung;Ryu, Sang-Burm;Lee, Sang-Gyu;Ryu, Heung-Gyoon
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.29 no.4
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    • pp.299-307
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    • 2018
  • Considering a nonlinear high power amplifier(HPA) and a predistorter, we have designed a four-dimensional 8-ary phase shift keying trellis-coded modulation(4D-8PSK-TCM) system, which is recommended for X-band satellite communications. Subsequently, we have evaluated and analyzed the spectrum, constellation characteristics, and BER performance of the system. In satellite communications, owing to the limited power, nonlinear characteristics that determine the operating point of the HPA must be analyzed because the HPA consumes high power. We herein report the design of the 4D-8PSK-TCM system, with efficiencies of 2 and 2.25 bits/channel-symbol. The simulation results confirmed that a 0.35 roll-off value is effective, considering the low peak-to-average power ratio(PAPR) characteristic and the narrow occupation bandwidth of the spectrum. It also confirmed that approximately 15~20 dB of output backoff(OBO) value is required at the HPA when the predistorter is not used, and approximately 1 dB of the OBO value is required when the predistorter is used.

A Study on the Analysis Technique of Sequence Landscaping through the Application and Development of Visual Amount Calculation Program of Landscapes (경관의 시각량 산출 프로그램 개발과 적용을 통한 연속경관 시퀀스 분석기법 연구)

  • Koo, Min-Ah
    • Journal of the Korean Institute of Landscape Architecture
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    • v.44 no.5
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    • pp.12-25
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    • 2016
  • In this study, in order to facilitate analysis in a continuous sequence, including the concept of the landscape experience time, countless frames of a continuous landscape were extracted. The amount of visual elements in each frame was data-converted numerically to take advantage of the quantitative data necessary for landscape planning and design was calculated in the rhythm of the sequence. In Order to shoot video with the flow of the line of sight of experience in landscape districts and landscape control points along the landscape corridor which is a continuous path, each of the corresponding computer motion techniques. This study developed a CRVP Koo computer program to effectively calculate the continuous visual number of specific landscape components by extracting uncounted frames at regular intervals, and after verifying, attempting to apply this to the target site. Through the applied result, it was possible to extract the digitized quantitative rhythm for each component of each landscape, the margin of error is very small when compared with the results of manual in photoshop, it was able to overcome the drawbacks of the manual. Using the rhythm of the derived sequence, and those close to the experience of the landscape, it was possible to achieve quantitative analysis derived from a variety of perspectives as well as was possible to be used as quantitative basis data and analysis technique for landscape planning and design.