• Title/Summary/Keyword: description logics

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Analysis and Modeling of Semantic Relationships in e-Catalog Domain (전자카탈로그에서의 의미적 관계 분석과 모델링)

  • Lee, Min-Jung;Lee, Hyun-Ja;Shim, Jun-Ho
    • The Journal of Society for e-Business Studies
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    • v.9 no.3
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    • pp.243-258
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    • 2004
  • Building a domain-suited ontology, as a means to implement the Semantic Web, is widely believed to offer users the benefit of exploiting the semantic knowledge constrained in the application. Electronic Catalog, shortly e-Catalog, manages the information about the goods or conditions play an important role in e-commerce domain. Consequently, semantically enriched yet precise information by the ontology may elaborate the business transactions. In this paper, we analyze the semantic relationships embodied within the catalog domain, as the first step towards the ontological modeling of e-catalog. Exploring ontology should leverage not only the representation of semantic knowledge but also provide the inferencing capability for the model. We employ the EER(extended Entity Relationships) for the basic model. Each modeling construct can be directly translated by DL(Description Logics). Semantic constraints that can be hardly represented in EER are directly modeled in DL.

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Toward Knowledge Preconditions for Composition of Semantic Web Services (시맨틱 웹서비스 조합을 위한 Knowledge Preconditions)

  • 김상균;이규철
    • Proceedings of the Korean Information Science Society Conference
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    • 2004.10b
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    • pp.247-249
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    • 2004
  • 그동안 planning 분야에서는 action 또는 plan이 epistemically feasible한지에 대한 Knowledge Preconditions(KP) 문제(1)를 다루기 위해 여러 연구들이 제안되었다. 하지만 기존 연구에서는 feasibility에 대한 검사를 design-time에만 수행하며 run-time에서 수행하지 않기 때문에 여러 agent의 트랜잭션들이 발생하는 웹서비스 조합(WSC : Web Services Composition)에서는 문제가 발생하게 된다. 따라서 본 논문에서는 이 문제(Interfering Agent Problem)를 해결하기 위해 transactionally feasible한 WSC를 정의하고 WSC의 atomicity를 보장하기 위한 방법을 제안한다. 뿐만 아니라 WSC를 표현하기 위해 Description Logics기반의 TL-ALCF(2)를 적용하여 시맨틱 웹의 온톨로지(OWL-S)와 성능이 좋은 기존 subsumption 프로시저를 그대로 이용할 수 있도록 한다.

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Design of the Space Vector Modulation of Servo System using VHDL (VHDL을 이용한 서보시스템의 공간벡터 변조부 설계)

  • 황정원;박승엽
    • Proceedings of the IEEK Conference
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    • 2001.06e
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    • pp.5-8
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    • 2001
  • In this paper, we have space vector PWM(Pulse Width Modulation) circuits on the FPGA(Field Programmable Gate Arry) chip designed by VHDL(Very high speed integrated circuit Hardware Description Language). This circuit parts was required at controlling the AC servo motor system and should have been designed with many discrete digital logics. In the result of this study, peripheral circuits are to be simple and the designed logic terms are robust and precise. Because of it's easy verification and implementation, we could deduced that the customize FPGA chip show better performance than that of circuit modules parts constituted of discrete IC.

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Ontological Modeling of E-Catalogs using Description Logic (Description Logic을 이용한 전자카타로그 온톨로지 모델링)

  • Lee Hyunja;Shim Junho
    • Journal of KIISE:Databases
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    • v.32 no.2
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    • pp.111-119
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    • 2005
  • Electronic catalog contains ich semantics associated with products, and serves as a challenging practical domain for ontology application. Ontology is concerned with the nature and relations of being. It can play a crucial role in e-commerce as a formalization of e-Catalogs. Description Logics provide a theoretical core for most of the current ontology languages. In this paper, we present an ontological model of e-Catalogs in DL. We take an Extended Entity Relationship approach for conceptual modeling method, and present the fundamental set of modeling constructs and corresponding description language representation for each construct. Additional semantic knowledge can be represented directly in DL. Our modeling language stands within SHIQ(d) which is known reasonably practical with regard to its expressiveness and complexity. We illustrate sample scenarios to show how our approach may be utilized in modeling e-Catalogs, and also implement the scenarios through a DL inference tool to see the practical feasibility.

A MDA-based Approach to Developing UI Architecture for Mobile Telephony Software (MDA기반 이동 단말 시스템 소프트웨어 개발 기법)

  • Lee Joon-Sang;Chae Heung-Seok
    • The KIPS Transactions:PartD
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    • v.13D no.3 s.106
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    • pp.383-390
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    • 2006
  • Product-line engineering is a dreaming goal in software engineering research. Unfortunately, the current underlying technologies do not seem to be still not much matured enough to make it viable in the industry. Based on our experiences in working on mobile telephony systems over 3 years, now we are in the course of developing an approach to product-line engineering for mobile telephony system software. In this paper, the experiences are shared together with our research motivation and idea. Consequently, we propose an approach to building and maintaining telephony application logics from the perspective of scenes. As a Domain-Specific Language(DSL), Menu Navigation Viewpoint(MNV) DSL is designed to deal with the problem domain of telephony applications. The functional requirements on how a set of telephony application logics are configured can be so various depending on manufacturer, product concept, service carrier, and so on. However, there is a commonality that all of the currently used telephony application logics can be generally described from the point of user's view, with a set of functional features that can be combinatorially synthesized from typical telephony services(i.e. voice/video telephony, CBS/SMS/MMS, address book, data connection, camera/multimedia, web browsing, etc.), and their possible connectivity. MNV DSL description acts as a backbone software architecture based on which the other types of telephony application logics are placed and aligned to work together globally.

A Term-based Language for Resource-Constrained Project Scheduling and its Complexity Analysis

  • Kutzner, Arne;Kim, Pok-Son
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.12 no.1
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    • pp.20-28
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    • 2012
  • We define a language $\mathcal{RS}$, a subclass of the scheduling language $\mathcal{RS}V$ (resource constrained project scheduling with variant processes). $\mathcal{RS}$ involves the determination of the starting times for ground activities of a project satisfying precedence and resource constraints, in order to minimize the total project duration. In $\mathcal{RS}$ ground activities and two structural symbols (operators) 'seq' and 'pll' are used to construct activity-terms representing scheduling problems. We consider three different variants for formalizing the $\mathcal{RS}$-scheduling problem, the optimizing variant, the number variant and the decision variant. Using the decision variant we show that the problem $\mathcal{RS}$ is $\mathcal{NP}$-complete. Further we show that the optimizing variant (or number variant) of the $\mathcal{RS}$-problem is computable in polynomial time iff the decision variant is computable in polynomial time.

Medusa: An Extended DL-Reasoner for SWRL-enabled Ontologies (Medusa: 시맨틱 웹 규칙 언어 처리를 위한 확장형 서술 논리 추론기)

  • Kim, Je-Min;Park, Young-Tack
    • Journal of KIISE:Software and Applications
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    • v.36 no.5
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    • pp.411-419
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    • 2009
  • In order to derive hidden Information (concept subsumption, concept satisfiability and realization) of OWL ontologies, a number of OWL reasoners have been introduced. Most of the reasoners were implemented to be based on tableau algorithm. However this approach has certain limitation. This paper presents architecture for Medusa. The Medusa is an extended DL-reasoner for SWRL(Semantic Web Rule Language) reasoning under well-founded semantics with ontologies specified in Description Logic. Description logic based ontology reasoners theoretically explore knowledge representation and its reasoning in concept languages. However these logics are not equipped with rule-based reasoning mechanisms for assertional knowledge base; specifically, rule and facts in logic programming, or interaction of rules and facts with terminology. In order to deal with the enriched reasoning, The Medusa provides combining DL-knowledge base and rule based reasoner. The described prototype uses $Prot{\acute{e}}g{\acute{e}}$ API[1] for controlling communication with the ontology reasoner.

Design and Implementation of the Dual Motor Drive AGV Controller Using CPLD (CPLD를 이용한 이륜 속도차방식 AGV 제어기 설계 및 구현)

  • 진중호;백한석;한석붕
    • Proceedings of the Korea Institute of Convergence Signal Processing
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    • 2000.12a
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    • pp.209-212
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    • 2000
  • This paper describes the design and implementation of a hard- wired AGV controller using CPLD(Complex Programmable Logic Device). The proposed controller manages a guidance equipment, motor and I/O sequence controller for a self-control traveling. Compared with a conventional $\mu$-processor, the CPLD controller using a hard-wired control method can reduce a difficult programming process. Also, the total costs of production are reduced, such as development time, product's size and difficulty because memory, combinational logic and sequential logics are implemented by CPLD. The Controller designed using behavioral description method with VHDL and was synthesized by MAX+Plus II of the ALTERA co. We implemented controller using EPF10K10LC84-4 device.

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Boosting the Reasoning-Based Approach by Applying Structural Metrics for Ontology Alignment

  • Khiat, Abderrahmane;Benaissa, Moussa
    • Journal of Information Processing Systems
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    • v.13 no.4
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    • pp.834-851
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    • 2017
  • The amount of sources of information available on the web using ontologies as support continues to increase and is often heterogeneous and distributed. Ontology alignment is the solution to ensure semantic interoperability. In this paper, we describe a new ontology alignment approach, which consists of combining structure-based and reasoning-based approaches in order to discover new semantic correspondences between entities of different ontologies. We used the biblio test of the benchmark series and anatomy series of the Ontology Alignment Evaluation Initiative (OAEI) 2012 evaluation campaign to evaluate the performance of our approach. We compared our approach successively with LogMap and YAM++ systems. We also analyzed the contribution of our method compared to structural and semantic methods. The results obtained show that our performance provides good performance. Indeed, these results are better than those of the LogMap system in terms of precision, recall, and F-measure. Our approach has also been proven to be more relevant than YAM++ for certain types of ontologies and significantly improves the structure-based and reasoningbased methods.

A Cadence SMV Based Formal Verification Method for Combinational Logics Written in Verilog HDL (Verilog HDL로 기술된 조합 논리회로의 Cadence SMV 기반 정형 검증 방법)

  • Jo, Seong-Deuk;Kim, Young-Kyu;Moon, Byungin;Choi, Yunja
    • Proceedings of the Korea Information Processing Society Conference
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    • 2015.10a
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    • pp.1027-1030
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    • 2015
  • 하드웨어 디자인 설계에서 초기 단계의 설계 오류 발견은 개발 비용 감소 및 설계 시간 단축 측면에서 그 효과가 매우 크다. 이러한 초기 설계 오류 발견을 위한 대표적인 방법으로는 정형 검증(formal verification)이 있으며, Cadence SMV(Symbolic Model Verifier)는 정형 검증을 위해 Verilog HDL(Hardware Description Language)을 SMV로 자동 변환 해주는 장점이 있지만, 사건 기반 구조(event based structures)의 sensitivity list에 대한 지원을 하지 않는 한계가 있다. 이에 본 논문에서는 Cadence SMV에서 디지털회로(digital circuit) 중 하나인 조합 논리회로(combinational logic circuit)를 sensitivity list가 고려된 검증이 가능하도록 하는 방법을 제안한다. 신뢰성 있는 실험을 위해 본 논문에서는 제안하는 방법의 일반적인 규칙을 도출하였고, 도출된 규칙이 적용된 SMV 파일을 생성하는 자동화 프로그램을 구현하여 실험하였다. 실험결과 제안한 방법을 적용한 경우 기존 Cadence SMV가 발견하지 못한 설계상의 오류를 발견할 수 있었다.