• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10C
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• pp.1433-1443
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• 2004

The power line modem proposed in this paper transmits the remote control signal using CSK(Code Shift Keying) and DS/SS method. The CSK technique provides the increased capacity of transmission and robustness towards noise. Besides, the DS/SS technique provides protection against narrow-band Gaussian interference and multi-path interference. The modem supports full-duplex communication using FDD(Frequency Division Duplex) and the modem structure for forward link is same with that for reverse link. To switch each sub-controlled unit smoothly, 4/$\pi$-DQPSK is adopted for noncoherent demodulation. The PN code for spreading spectrum seues to divide each group which consists of sub-controlled units and Walsh code is used for the M-ary CSK technique. Each block is designed and verified with TMS320C5402 DSP. We show the superiority of the proposed method by analyzing numerically the system performance for the factors of the DS/SS and CSK method ullder additive white Gaussian noise and PBI.

• Journal of IKEEE
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• v.26 no.1
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• pp.27-35
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• 2022

This paper proposes an ultrasound vessel-pattern imaging algorithm with low computational complexity. The proposed imaging algorithm reconstructs blood-vessel patterns by only detecting blood flow, and can be applied to a real-time signal processing hardware that extracts an ultrasonic finger-vessel pattern. Unlike a blood-flow imaging mode of typical ultrasound medical imaging device, the proposed imaging algorithm only reconstructs a presence of blood flow as an image. That is, since the proposed algorithm does not use an I/Q demodulation and detects a presence of blood flow by accumulating an absolute value of the clutter-filter output, a structure of the algorithm is relatively simple. To verify a complexity of the proposed algorithm, a simulation model for finger vessel was implemented using Field-II program. Through the behavioral simulation, it was confirmed that the processing time of the proposed algorithm is around 54 times less than that of the typical color-flow mode. Considering the required main building blocks and the amount of computation, the proposed algorithm is simple to implement in hardware such as an FPGA and an ASIC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.430-439
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• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.

• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.141-148
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• 2004

Recently, the demand of broadband communications such as high-speed internet, HDTV, 3D-HDTV and ATM backbone network has been increased drastically. For transmitting the broad-bandwidth data using wireless network, it is needed to use ka-band frequency. However, the use of this ka-band frequency is seriously affected to the received data performance by rain fading and atmospheric propagation loss at the Ka-band satellite communication link. So, we need adaptive MODEM to endure the degraded performance by channel environment. In this paper, we will present the structure and design of the 155Mbps adaptive Modem adaptively compensated against channel environment. In order to compensate the rain attenuation over the ka-band wireless channel link, the adaptive coding schemes with variable coding rates and the multiple modulation schemes such as trellis coded 8-PSK, QPSK, and BPSK are adopted. And the blind demodulation scheme is proposed to demodulate without Information of modulation mode at the multi-mode demodulator, and the fast phase ambiguity resolving scheme is proposed. The design and simulation results of adaptive Modem by SPW model are provided. This 155Mbps adaptive MODEM was designed and implemented by single ASIC chip with the $0.25\mu{m}$ CMOS standard cell technology and 950 thousand gates.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.253-256
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• 2009

This paper describes a core generator (FFT_Core_Gen) which generates Verilog HDL models of 8 different FFT/IFFT cores with $N=64{\times}2^k$($0{\leq}k{\leq}7$ for OFDM-based communication systems. The generated FFT/IFFT cores are based on in-place single memory architecture, and use a hybrid structure of radix-4 and radix-2 DIF algorithm to accommodate various FFT lengths. To achieve both memory reduction and the improved SQNR, a conditional scaling technique is adopted, which conditionally scales the intermediate results of each computational stage, and the internal data and twiddle factor has 14 bits. The generated FFT/IFFT cores have the SQNR of 58-dB for N=8,192 and 63-dB for N=64. The cores synthesized with a $0.35-{\mu}m$ CMOS standard cell library can operate with 75-MHz@3.3-V, and a 8,192-point FFT can be computed in $762.7-{\mu}s$, thus the cores satisfy the specifications of wireless LAN, DMB, and DVB systems.