• Journal of Advanced Navigation Technology
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• v.15 no.2
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• pp.227-233
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• 2011

This paper presents a small-area ISDB-T time deinterleaver structure. ISDB-T is an mobile TV standard that is widely used in Japan and many South American countries. One of the strong points of the standard is the long interleaving depth, which enhance the communication performance. However, long interleaving requires many delay buffers, in other words many pointer registers. This paper reduces the number of pointer registers with the deinterleaver equivalent transformation. The experimental results show that the area is reduced with the proposed structure.

• Journal of Advanced Navigation Technology
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• v.15 no.2
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• pp.221-226
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• 2011

This paper presents a DTMB deinterleaver structure to reduce SDRAM power consumption. DTMB, the Chinese digital TV standard, has a deinterleaver that consists of many long delay buffers. SDRAM is used for this deinterleaver. The proposed structure pairs data and transfer a pair with an SDRAM transfer. With the reduction of the SDRAM operation number, the proposed structure can save the SDRAM power consumption by around 35%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1135-1140
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• 2011

This paper proposes a DTMB deinterleaver structure to reduce the SDRAM power consumption with buffer conversion and the single pointer-register structure. The DTMB deinterleaver with deep interleaving for higher performance consists of long delay buffers allocated on SDRAM. The conventional structure activates a new SDRAM row almost everytime when it reads and writes a datum. In the proposed structure, long buffers are transformed into several short buffers so that the number of row activations is reduced. The single pointer-register structure solves the problem of many pointer-registers. The experimental results show that the SDRAM power consumption can be reduced to around 37% with slight logic area reduction.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.6
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• pp.718-726
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• 2002

This paper presents a novel Viterbi decoding architecture for European Digital Video Broadcasting (DVB) receiver. The channel sate information (CSI) of each sub carrier is used to weight the bit-metric of each symbol. The weighted bit-metric is delivered to Viterbi decoder after going through the symbol deinterleaver and bit deinterleaver, such that the CSI can be correctly applied to corresponding bits even after the two interleavings. Simulation shows that the new architecture gives significant performance enhancement of 6~13dB in Rayleigh fading channels depending on the modulation types. This results is also better than previous results by 3.7~10.3dB.

• Information and Communications Magazine
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• v.12 no.6
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• pp.88-100
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• 1995

본 고에서는 디지털 위성방송 시스템의 구성요소중 channel부의 구조 및 기능분석을 국내 디지털 DBS를 기준으로 설명하였다. channel부는 channel coding과 modulation 기능을 수행한다. Channel coding은 Reed Solomon code, interleaving, convolutional code를 연집하여 사용하고, modulation은 QPSK와 raised cosine pulse shaping을 한다. 수신기의 channel부는 antenna, LNB, tuner, QPSK 복조기, Viterbi, deinterleaver, RS decoder로 구성되어있다.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.289-292
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• 2004

In this paper, we propose parallel Viterbi decoders applied to UWB(Ultra Wide Band). In consideration of power dissipation and ease of design, we design the architecture, using 132MHz clock instead of 528MHz clock in Baseband. Because Deinterleaver writes and reads the transmitted data per 6Ncbps(The number of coded bits per symbol). using the difference between the number of sampling clock per symbol and the number of coded bits per symbol, we reduce performance degradation of parallel Viterbi decoders. In comparison with using 528MHz clock, the result is little difference.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2470-2472
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• 1998

In this paper, we proposed the method to improve the performance of Viterbi decoder by applying Concatenated structure. Proposed decoder for Concatenated Code is designed with inner Viterbi decoder, block deinterleaver and outer Viterbi decoder. Inner Viterbi decoder (K=7, R=1/2) has 8-level soft decision, but outer decoder (K=7, R= 1/2) has 2-level hard decision. Applied interleaving scheme make decoder to have better BER performance in Concatenated code. The designed VLSI shares inner decoder with outer decoder. Because of sharing structure, complexity of decoder can be reduced to half. But it required about twice clock speed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.6 s.97
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• pp.556-562
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• 2005

In this paper, we propose interleaved super-orthogonal convolutional coded ultra wide-band impulse radio(ISOC-UWB-IR) system, and analyze its performance. The proposed system uses interleaver and deinterleaver to decorrelate the temporal correlation of the fading process and to obtain the diversity gain. We also suggest the three types of interleavers, which are pulse-wise interleaver(PI), pulse sub-group-wise interleaver(PSGI), and pulse group-wise interleaver(PGI). Performance analysis result shows that the interleaving scheme, rather than the code rate of super orthogonal convolutional code(SOC) encoder, affects the performance for the Rayleigh fading channel.

• ETRI Journal
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• v.31 no.6
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• pp.795-802
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• 2009

This paper presents the design of an advanced terrestrial digital multimedia broadcasting (AT-DMB) baseband receiver SoC. The AT-DMB baseband is incorporated into a hierarchical modulation scheme consisting of high priority (HP) and low priority (LP) stream decoders. The advantages of the hierarchical modulation scheme are backward compatibility and an enhanced data rate. The structure of the HP stream is the same as that of the conventional T-DMB system; therefore, a conventional T-DMB service is possible by decoding multimedia data in an HP stream. An enhanced data rate can be achieved by using both HP and LP streams. In this paper, we also discuss a time deinterleaver that can deinterleave data for a time duration of 384 ms or 768 ms. The interleaving time duration is chosen using the LP symbol mapping scheme. Furthermore, instead of a Viterbi decoder, a turbo decoder is adopted as an inner error correction system to mitigate the performance degradation due to a smaller symbol distance in a hierarchically modulated LP symbol. The AT-DMB baseband receiver SoC is fabricated using 0.13 ${\mu}m$ technology and shows successful operation with a 50 mW power dissipation.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.81-88
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• 2004

In this paper, we designed the outer encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes (16 bytes) from the input packet (188by1e) of MPEG-2 TS and the encoded data was distributed output by the convolutional interleaver for Preventing burst errors. In the decoder part, It was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8 bytes in a packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.