• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.33-36
• /
• 2001

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The rise throughput and the stability in the device fabrication can be obtained by applying of CMP process to STI structure in 0.18$\mu\textrm{m}$ m semiconductor device. The reverse moat process has been added to employ in of each thin films in STI-CMP was not equal, hence the devices must to be effected, that is, the damage was occurred in the device area for the case of excessive CMP process and the nitride film was remained on the device area for the case of insufficient CMP process, and than, these defects affect the device characteristics. Also, we studied the High Selectivity Slurry(HSS) to perform global planarization without reverse moat step.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.15 no.10
• /
• pp.838-843
• /
• 2002

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The reverse moat etch process has been used for the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process with conventional low selectivity slurries. Thus, the process became more complex, and the defects were seriously increased. In this paper, we studied the direct STI-CMP process without reverse moat etch step using high selectivity slurry(HSS). As our experimental results show, it was possible to achieve a global planarization without the complicated reverse moat process, the STI-CMP process could be dramatically simplified, and the defect level was reduced. Therefore the throughput, yield, and stability in the ULSI semiconductor device fabrication could be greatly improved.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.445-446
• /
• 2008

With the semiconductor industry evolving into the deep sub-micron (DSM) era, the crosstalk effects on interconnect lines of a chip have increasingly caused a major bottleneck for design closure. In this paper, we propose an effective design guide line to reduce cell area overhead without crosstalk noise violations by using crosstalk prevention flow with clock shielding.

• The Magazine of the IEIE
• /
• v.30 no.9
• /
• pp.28-28
• /
• 2003

SoC(System on Chip)의 발전은 현재 널리 쓰이는 기존의 설계 방법론으로는 해결될 수 없는 여러 가지 문제들을 생성하고 있다. 제품의 복잡도는 급격히 증가하는 반면 제품 수명은 지속적으로 감소하고 있으며, 기존 구현 기술의 향상만으로는 해결하기 쉽지 않은 VDSM (Very Deep Sub-Micron) 문제 또한 새로이 도출되고 있는 실정이다. 이러한 문제들은 적기에 시장에 제품을 출시하는 데에 많은 어려움을 끼치게 되기 때문에, 기존의 방법론을 뛰어 넘는 새로운 설계 방법론을 위한 많은 연구들이 활발히 진행되고 있다. 이러한 방법론 중 효율적인 한 방안으로 "재사용"의 개념이 대두되고 있으며, platform-based design은 이러한 재사용의 개념을 SoC 설계에 효율적으로 적용할 수 있는 방법으로 많은 관심을 받고 있다. 본 논문은 이러한 platform-based design의 최근 동향 및 현재 삼성전자에서 추진하고 있는 platform-based design에 대해 기술한다.

• The Magazine of the IEIE
• /
• v.30 no.9
• /
• pp.934-941
• /
• 2003

SoC(System on Chip)의 발전은 현재 널리 쓰이는 기존의 설계 방법론으로는 해결될 수 없는 여러 가지 문제들을 생성하고 있다. 제품의 복잡도는 급격히 증가하는 반면 제품 수명은 지속적으로 감소하고 있으며, 기존 구현 기술의 향상만으로는 해결하기 쉽지 않은 VDSM (Very Deep Sub-Micron) 문제 또한 새로이 도출되고 있는 실정이다. 이러한 문제들은 적기에 시장에 제품을 출시하는 데에 많은 어려움을 끼치게 되기 때문에, 기존의 방법론을 뛰어 넘는 새로운 설계 방법론을 위한 많은 연구들이 활발히 진행되고 있다. 이러한 방법론 중 효율적인 한 방안으로 "재사용"의 개념이 대두되고 있으며, platform-based design은 이러한 재사용의 개념을 SoC 설계에 효율적으로 적용할 수 있는 방법으로 많은 관심을 받고 있다. 본 논문은 이러한 platform-based design의 최근 동향 및 현재 삼성전자에서 추진하고 있는 platform-based design에 대해 기술한다.

• Proceedings of the IEEK Conference
• /
• 2002.07c
• /
• pp.1724-1727
• /
• 2002

Asynchronous circuits have the potential to solve the problems related to parameter variations such as gate delays in deep sub-micron technologies. However, current CAD tools for large-scale asyn-chronous circuits partition specification irrelevantly, because these tools cannot control the granularity of circuit decomposition. In this paper we propose a hierarchical Control/Data Flow Graph (CDFG) containing nodes that are flexibly partitioned or merged into other nodes. We show a partitioning algorithm for such CDFGs to generate handleable Signal Transition Graphs (STGs) for asynchronous synthesis tools. The algorithm a1lows designers to assign the maximum number of signals of partitioned nodes considering of timality. From an experiment, this algorithm can flexibly partition and result in more compact asynchronous controllers.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.26 no.11
• /
• pp.1747-1750
• /
• 2022

As shrinking the semiconductor process into the deep sub-micron to achieve high-density, low power and high performance integrated circuits, MBU (multiple bit upset) by soft errors is one of the major challenge of on-chip memory systems. To address the MBU, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not resolve mis-correction. We propose the SEC-DED-DAEC-TAED(triple adjacent error detection) code without mis-corrections. The generated H-matrix by the proposed heuristic algorithm to accomplish the proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the 2-stage pipelined decoder can be employed on-chip memory system.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.3
• /
• pp.331-340
• /
• 2012

In the deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. Spare columns are often included in memories to repair defective cells or bit lines during production test. In many cases, the repair process will not use all spare columns. Schemes have been proposed to exploit these unused spare columns to store additional check bits which can be used to reduce the miscorrection probability for triple errors in single error correction-double error detection (SEC-DED). These additional check bits increase the dimensions of the parity check matrix (H-matrix) requiring extra area overhead. A method is proposed in this paper to efficiently fill the extra rows of the H-matrix on the basis of similarity of logic between the other rows. Optimization of the whole H-matrix is accomplished through logic sharing within a feasible operating time resulting in reduced area overhead. A detailed implementation using fuse technology is also proposed in this paper.

• Journal of information and communication convergence engineering
• /
• v.6 no.2
• /
• pp.122-128
• /
• 2008

Multiprocessor architectures and platforms, such as, a multiprocessor system on chip (MPSoC) recently introduced to extend the applicability of the Moore's law, depend upon concurrency and synchronization in both software and hardware to enhance design productivity and system performance. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and non-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future System-on-Chip (SoC). We have modeled a concurrent architecture for a customizable and scalable NOC in a system level modeling environment using MLDesigner (from MLD Inc.). Varying network loads under various traffic scenarios were applied to obtain realistic performance metrics. We provide the simulation results for latency as a function of the buffer size. We have abstracted the area results for NOC components from its FPGA implementation. Modeled NOC architecture supports three different levels of quality-of-service (QoS).

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.525-526
• /
• 2008

This paper proposes a new high-speed level shifter using a special high voltage device with low threshold voltage. Also, novel low voltage swing method is proposed. The high voltage device is a standard LDMOS(Laterally Diffused MOS) device in a $0.18{\mu}m$ CMOS process without adding extra mask or process step to realize it. A level shifter uses 5V LDMOSs as voltage clamps to protect 1.8V NMOS switches from high voltage stress the gate oxide. Also, level-up transition from 1.8V to 5V takes only 1.5ns in time. These circuits do not consume static DC power, therefore they are very suitable for low-power and high-speed interfaces in the deep sub-quarter-micron CMOS technologies.