• Broadcasting and Media Magazine
• /
• v.15 no.4
• /
• pp.66-76
• /
• 2010

HEVC(High Efficiency Video Coding)는 현재 표준화가 진행되고 있는 새로운 비디오 부호화 표준의 가칭이다. 이 표준화에서는 H.264/AVC를 넘어선 높은 부호화 성능을 갖기 위해서 다양한 방법들이 논의되고 있으며, 그 중에서 deblocking filter 및 adaptive loop filter 기술에 대해 본 고에서 설명하고자 한다. 기술적으로 deblokcing 필터와 adaptive loop filter는 양자화 및 부호화 연산과 정에서 손실되는 정보를 줄이기 위해 복원된 영상에 필터링을 수행함으로써주관적화질을향상시키기위한기술이다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.11C
• /
• pp.662-672
• /
• 2011

This paper presents a new edge-preserving algorithm and its VLSI architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge-preserving maps. Based on these maps, a two-step adaptive filter which includes offset filtering and edge-preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory-reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is prototyped on FPGA Cyclone II, and then we estimated performance when the filter is synthesized on ANAM 0.25 ${\mu}m$ CMOS cell library using Synopsys Design Compiler. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details.

• The Journal of Korean Association of Computer Education
• /
• v.13 no.4
• /
• pp.77-86
• /
• 2010

In this paper, we propose a real time post-processing visual enhancement technique to reduce the blocking artifacts in block based DCT decoded image for mobile devices that have allocation of the restricted resource. In order to reduce the blocking artifacts effectively even while preserving the image edge to the utmost, the proposed algorithm uses the deblocking filtering or the directional filtering according to the edge detection of the each pixel. After it is discriminated that the pixel to apply the deblocking filtering belongs again to the monotonous area, the weighted average filter with the adaptive mask is applied for the pixel to remove the blocking artifacts. On the other hand, a new directional filter is utilized to get rid of staircase noise and preserve the original edge component. Experimental results show that the proposed algorithm produces better results than those of the conventional algorithms in both subjective and objective qualities.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.10 s.352
• /
• pp.45-53
• /
• 2006

In this paper, we proposed a parallel hardware architecture for deblocking filter in K264/AVC. The deblocking filter has high efficiency in H.264/AVC, but it also has high computational complexity. For real time video processing, we chose a two 1-D parallel filter architecture, and tried to reduce memory access using dual-port SRAM. The proposed architecture has been described in Verilog-HDL and synthesized on Hynix 0.25um CMOS Cell Library using Synopsys Design Compiler. The hardware size was about 27.3K logic gates (without On-chip Memory) and the maximum operating frequency was 100Mhz. It consumes 258 clocks to process one macroblock, witch means it can process 47.8 HD1080P(1920pixel* 1080pixel) frames per second. It seems that it can be used for real time H.264/AVC encoding and decoding of various multimedia applications.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.7
• /
• pp.52-60
• /
• 2008

The deblocking filter in the H.264/AVC video coding standard helps to reduce the blocking artifacts produced in the decoding process. But it consumes one third of the computational complexity in H.624/AVC decoder, which advocates an efficient design of a hardware accelerator for filtering. This paper proposes an architecture of deblocking filter using two filters and some registers for data reuse. Our architecture improves the throughput and minimize the number of external memory access by increasing data reuse. After initialization, two filters are able to perform filtering operation simultaneously. It takes only 96 clocks to complete filtering for one macroblock. We design and synthesis our architecture using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 200MHz.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.47 no.2
• /
• pp.11-19
• /
• 2010

Most of deblocking filters assumes that the block boundaries are accurately known and the coding information like quantization parameters are available. In some applications such as commercial television, however, many external video inputs without known block boundary and coding information arc given. If a decompressed video sequence heavily degraded with blocking artifacts is given through the external video port, it is absolutely necessary to detect block boundaries and control the strength of deblocking filtering by analysing the given images. This paper presents an efficient method to find the block boundaries and estimate the strength of the blocking artifacts without the knowledge of coding information. In addition, the confidence of the estimated blocking artifact information is also evaluated to control the adaptive deblocking filter robustly. Experiment results show that the estimated block boundary locations and strength relative strength and confidence information are practically good enough to reduce the blocking artifacts without prior knowledge.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.11 no.3
• /
• pp.1700-1721
• /
• 2017

The problem of blocking artifacts is very common in block-based image and video compression, especially at very low bit rates. In this paper, we propose a post-processing method for JPEG-coded image deblocking via sparse representation and adaptive residual threshold. This method includes three steps. First, we obtain the dictionary by online dictionary learning and the compressed images. The dictionary is then modified by the histogram of oriented gradient (HOG) feature descriptor and K-means cluster. Second, an adaptive residual threshold for orthogonal matching pursuit (OMP) is proposed and used for sparse coding by combining blind image blocking assessment. At last, to take advantage of human visual system (HVS), the edge regions of the obtained deblocked image can be further modified by the edge regions of the compressed image. The experimental results show that our proposed method can keep the image more texture and edge information while reducing the image blocking artifacts.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.11 no.3
• /
• pp.1684-1699
• /
• 2017

The deblocking filter (DF) reduces blocking artifacts in encoded video sequences, and thereby significantly improves the subjective and objective quality of videos. Statistics show that the DF accounts for 5-18% of the total decoding time in high-efficiency video coding. Therefore, speeding up the DF will improve codec performance, especially for the decoder. In view of the rapid development of multicore technology, we propose a parallel DF scheme based on a modified order of accessing the coding tree units (CTUs) by analyzing the data dependencies between adjacent CTUs. This enables the DF to run in parallel, providing accelerated performance and more flexibility in the degree of parallelism, as well as finer parallel granularity. We additionally solve the problems of variable privatization and thread synchronization in the parallelization of the DF. Finally, the DF module is parallelized based on the HM16.1 reference software using OpenMP technology. The acceleration performance is experimentally tested under various numbers of cores, and the results show that the proposed scheme is very effective at speeding up the DF.

• ETRI Journal
• /
• v.32 no.3
• /
• pp.380-389
• /
• 2010

This paper presents a new edge-protection algorithm and its very large scale integration (VLSI) architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge-protection maps. Based on these maps, a two-step adaptive filter which includes offset filtering and edge-preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory-reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is verified on FPGA Cyclone II and implemented using the ANAM 0.25 ${\mu}m$ CMOS cell library. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details. The PSNR performance of our algorithm using pixel classification is better than that of previous algorithms using block classification.

• ETRI Journal
• /
• v.29 no.3
• /
• pp.396-398
• /
• 2007

This letter presents an architecture based on a new double-filter strategy to perform the adaptive in-loop filtering process specified by the H.264/AVC standard. The proposed architecture shows considerable advantages, both in terms of hardware cost and latency, when compared with the approaches found in the most recent literature.