• Proceedings of the Korean Information Science Society Conference
• /
• 2003.04a
• /
• pp.599-601
• /
• 2003

pull 기반의 데이터 방송 환경에서는 클라이언트의 데이터 요청을 최소화하기 위하여 캐쉬의 도입이 특히 필요하다. 이러한 환경에서 캐쉬의 도입 효과를 극대화하기 위해서는 히트율 뿐만 아니라 미스 비용도 고려한 효율적인 캐쉬 대체 전략의 수립이 무엇보다도 시스템 성능에 중요한 영향을 미친다. 본 논문에서는 클라이언트의 데이터 액세스 빈도수 및 대기 시간 등을 고려하면서 최신성을 합께 반영하는 캐쉬 대체 전략을 제안한다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2008.11a
• /
• pp.1303-1306
• /
• 2008

전체 웹 트래픽 요소 중 가장 큰 비중을 차지하는 HTTP 트래픽을 대상으로 하여 과거의 데이터와 비교 분석해 보았다. 현재의 웹 페이지의 경우 최소 10개~ 20개 이상의 또 다른 객체를 요청 하게 되고 있음을 발견했다. 이는 텍스트가 주를 이루었던 과거의 객체들과 매우 다른 양상을 보인다. 최근의 웹 트레이스 로그를 분석하여 기존 알고리즘들의 문제점을 발견하여 지적 하며 새로운 캐싱 알고리즘의 개념을 제안한다.

• KIPS Transactions on Computer and Communication Systems
• /
• v.10 no.10
• /
• pp.277-284
• /
• 2021

Recently, the smart home environment is expected to be a platform that collects, integrates, and utilizes various data through convergence with wireless information and communication technology. In fact, the number of smart devices with various sensors is increasing inside smart homes. The amount of data that needs to be processed by the increased number of smart devices is also increasing, and big data processing systems are actively being introduced to handle it effectively. However, traditional big data processing systems have all requests directed to cluster drivers before they are allocated to distributed nodes, leading to reduced cluster-wide performance sharing as cluster drivers managing segmentation tasks become bottlenecks. In particular, there is a greater delay rate on smart home devices that constantly request small data processing. Thus, in this paper, we design a Apriori-based big data system for effective data processing in smart home environments where frequent requests occur at the same time. According to the performance evaluation results of the proposed system, the data processing time was reduced by up to 38.6% from at least 19.2% compared to the existing system. The reason for this result is related to the type of data being measured. Because the amount of data collected in a smart home environment is large, the use of cache servers plays a major role in data processing, and association analysis with Apriori algorithms stores highly relevant sensor data in the cache.

• Spatial Information Research
• /
• v.11 no.3
• /
• pp.261-274
• /
• 2003

The effective probability-based tile pre-fetching algorithm and the collaborative cache replacement algorithm are able to reduce the response time for user's requests by transferring tiles which will be used in advance and determining tiles which should be removed from the restrictive cache space of a client based on the future access probabilities in Web GISs(Geographical Information Systems). The Web GISs have multi-level abstracted data for the quick response time when zoom-in and zoom-out queries are requested. But, the previous pre-fetching algorithm is applied on only two-dimensional pre-fetching space, and doesn't consider expanded pre-fetching space for multi-level abstracted data in Web GISs. In this thesis, a probability-based pre-fetching algorithm for multi-level abstracted in Web GISs was proposed. This algorithm expanded the previous two-dimensional pre-fetching space into three-dimensional one for pre-fetching tiles of the upper levels or lower levels. Moreover, we evaluated the effect of the proposed pre-fetching algorithm by using a simulation method. Through the experimental results, the response time for user requests was improved 1.8%∼21.6% on the average. Consequently, in Web GISs with multi-level abstracted data, the proposed pre-fetching algorithm and the collaborative cache replacement algorithm can reduce the response time for user requests substantially.

• International Journal of Internet, Broadcasting and Communication
• /
• v.12 no.4
• /
• pp.109-121
• /
• 2020

As a decrease in labor became a serious issue in the manufacturing industry, smart factory technology, which combines IT and the manufacturing business, began to attract attention as a solution. In this study, we have designed and implemented a real-time remote management system for smart factories, which is connected to an IoT sensor and gateway, for plastic manufacturing plants. By implementing the REST API in which an IoT sensor and smart gateway can communicate, the system enabled the data measured from the IoT sensor and equipment status data to the real-time monitoring system through the gateway. Also, a web-based management dashboard enabled remote monitoring and control of the equipment and raw material processing status. A comparative analysis experiment was conducted on the suggested system for the difference in processing speed based on equipment and measurement data number change. The experiment confirmed that saving equipment measurement data using cache mechanisim offered faster processing speed. Through the result our works can provide the basic framework to factory which need implement remote management system.

• Transactions on Electrical and Electronic Materials
• /
• v.16 no.6
• /
• pp.293-302
• /
• 2015

Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.10 no.7
• /
• pp.3231-3244
• /
• 2016

As processor design has been transiting from homogeneous multicore processor to heterogeneous multicore processor, traditional Amdahl's law cannot meet the new challenges for asymmetric multicore system. In order to further investigate the impact factors related to the Overhead of Data Preparation (ODP) for Asymmetric multicore systems, we evaluate an asymmetric multicore system built with CPU-GPU by measuring the overheads of memory transfer, computing kernel, cache missing and synchronization. This paper demonstrates that decreasing the overhead of data preparation is a promising approach to improve the whole performance of heterogeneous system.

• The KIPS Transactions:PartA
• /
• v.16A no.2
• /
• pp.113-124
• /
• 2009

With increasing multicore system, much effort has been put on the performance improvement of its application. Because multicore system has multiple processing devices in one system, its processing power increases compared to the single core system. However in many cases the advantages of multicore can not be exploited fully because the existing software and hardware were designed to be suitable for single core. When the existing software runs on multicore, its performance improvement is limited by the bottleneck of sharing resources and the inefficient use of cache memory on multicore. Therefore, according as the number of core increases, it doesn't show performance improvement and shows performance drop in the worst case. In this paper we propose a method of performance improvement of multicore system by applying Flow-Level Parallelism to the existing TCP/IP network application and operating system. The proposed method sets up the execution environment so that each core unit operates independently as much as possible in network application, TCP/IP stack on operating system, device driver, and network interface. Moreover it distributes network traffics to each core unit through L2 switch. The proposed method allows to minimize the sharing of application data, data structure, socket, device driver, and network interface between each core. Also it allows to minimize the competition among cores to take resources and increase the hit ratio of cache. We implemented the proposed methods with 8 core system and performed experiment. Experimental results show that network access speed and bandwidth increase linearly according to the number of core.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.2B
• /
• pp.129-137
• /
• 2003

Multimedia streams, like MPEG continuously retrieve multimedia data because of their incessant playback. While these streams need an efficient support of kernel, the current buffer cache mechanism of Linux kernel such as Unix operating system was designed apt for small files, which is aperiodically requested as well as time uncritical. But, in case of continuous media, the CPU must enormously copy memory from kernel address space to user address space. This must lead to a large CPU overhead. This overhead both degrades system throughput and cannot guarantee QOS. In this paper, we have designed and implemented two memory copy reduction schemes in Linux kernel, direct I/O and one copy. The direct I/O skips the buffer cache layer of Linux kernel and results in dramatic reduction of CPU memory copy overhead. And, the one copy provides a fast disk-to-network data path without copying to user address space. The experimental results show considerable reduction of CPU overhead and throughput improvements.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.5
• /
• pp.71-80
• /
• 2004

This paper describes embedded processor architecture design which is applicable to multimedia in mobile platform The main description is based on basic processor architecture and consideration about energy efficiency when used in mobile platform To design processor data path architecture (pipeline, branch prediction, multiple issue superscalar, function unit number) which is optimal to multimedia application and cache hierarchy and its structure, we have nut the simulation with variant architecture using MPEG4 test bench as multimedia application. We analyzed energy efficiency of architecture to check if it is applicable to mobile platform and decide basic processor architecture based on analysis result. The suggested basic processor architecture not only can be applied to mobile platform but also can be applied to basic processor architecture of configurable processor which is designed through automatic design environment.