• The Journal of the Korea Contents Association
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• v.7 no.8
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• pp.21-30
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• 2007

Due to the growth of embedded systems and the development of semi-conductor and storage devices, digital convergence devises is ever growing. Digital convergence devices are equipments into which various functions such as communication, playing movies and wave files and electronic dictionarys are integrated. Example are portable multimedia players(PMPs), personal digital assistants(PDAs), and smart phones. Therefore, these devices need an efficient file system which manages and controls various types of files. In designing such file systems, the size constraint for small embedded systems as well as performance and compatibility should be taken into account. In this paper, we suggest the partial buffer cache technique. Contrary to the traditional buffer cache, the partial buffer cache is used for only the FAT meta data and write-only data. Simulation results show that we could enhance the write performance more than 30% when the file size is larger than about 100 KBytes.

• Journal of KIISE:Information Networking
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• v.28 no.2
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• pp.251-261
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• 2001

The traffic on the Internet has been growing exponentially for some time. This growth is beginning to stress the current-day routers. However, switching technology offers much higher performance. So the label switching network which combines IP routing with switching technology, is emerged. EspeciaJJy in the data driven label switching, flow classification and cache table management are needed. Flow classification is to classify packets into switching and non-switching packets, and cache table management is to maintain the cache table which contains information for flow classification and label switching. However, the cache table management affects the performance of label switching network considerably as well as flowclassification because the bigger cache table makes more packet switched and maintains setup cost lower, but cache is restricted by local router resources. For that reason, there is need to study the cache replacement scheme for the efficient cache table management with the Internet traffic characterized by user. So in this paper, we propose several cache replacement schemes for label switching network. First, without the limitation at switching capacity in the router. we introduce FIFO(First In First Out). LFC(Least Flow Count), LRU(Least Recently Used! scheme and propose priority LRU, weighted priority LRU scheme. Second, with the limitation at switching capacity in the router, we introduce LFC-LFC, LFC-LRU, LRU-LFC, LRU-LRU scheme and propose LRU-weighted LRU scheme. Without limitation, weighted priority LRU scheme and with limitation, LRU-weighted LRU scheme showed best performance in this paper.

• Journal of Digital Contents Society
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• v.16 no.2
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• pp.257-262
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• 2015

Recently, the interests of mobile GIS technology is increasing with the spread of wireless network, the improvement of mobile device's performances, and the growth of demands about mobile services. Providing services in a wireless environment with existing wired-based GIS solutions have many limitations such as slow communication, processing rates and screen size. In this paper, we propose a cache algorithm on client side to solve the above problems. The proposed algorithm demonstrates the performance improvement over known studies by utilizing unit time and spatial proximity. In addition, this paper conducts a performance evaluation to measure the improvement in algorithm efficiency and analyzes the results of the performance evaluation. When spatial data queries are conducted, according to our performance evaluation, hit rate has been improved over the existing algorithms.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.2
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• pp.33-43
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• 1993

Lock mechanism is essential for synchronization on the multiprocessor systems. Lock mechanism needs to reduce the time for lock operation in low lock contention. Lock mechanism must consider the case of the high lock contention. The conventional lock control scheme in memory results in the increase of bus traffic and memory utilization in lock operation. This paper suggests a lock scheme which stores the lock data in cache and manages it efficiently to reduce the time spent in lock operation when the lock contention is low on a multiprocessor system built on HiPi-bus(Highly Pipelined bus). This paper also presents the design of the HIPi-CLOCK (Highly Pipelined bus Cache LOCK mechanism) which transfere the data from on cache to another when the lock contention is high. The designed simulator compares the conventional lock scheme which controls the lock in memory with the suggested HiPi-CLOCK scheme in terms of the RMW(Read-Modify-Write) operation time using simulated trace. It is shown that the suggested lock control scheme performance is over twice than that of the conventional method in low lock contention. When the lock contention is high, the performance of the suggested scheme increases as the number of the shared lock data increases.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.4
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• pp.143-149
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• 2012

MANET is a network that is a very useful application to build network environment in difficult situation to build network infrastructure. But, nodes that configures MANET have difficulties in data retrieval owing to resources which aren't enough and mobility. Therefore, caching scheme is required to improve accessibility and availability for frequently accessed data. In this paper, we proposed a technique that utilize mobility prediction of nodes to retrieve quickly desired information and improve data availability. Mobility prediction of modes is performed through distance calculation using location information. We used technique which global cluster table and local member table is managed by cluster head to reduce data consistency and query latency time. We compared COCA and CacheData and experimented to confirm performance of proposed scheme in this paper and efficiency of the proposed technique through experience was confirmed.

• Journal of KIISE:Information Networking
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• v.27 no.2
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• pp.149-159
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• 2000

In mobile computing environments, invalidation and propagation method based on broadcasting is used to transmit the information for cache maintenance of mobile hosts. Previous researches generally adopted invalidation method that easily adapts to the limited network bandwidth and the frequent disconnection. But the invalidation of frequently accessed data causes the contention on the wireless network with the increasing cache requests. Although the propagation method can reduce the cache requests, the high probability of broken message or loss of message is the main factor that degrades the system performance. To resolve these problems, we propose adaptive cache maintenance scheme that dynamically adjusts the broadcasting ratio of invalidation and propagation, according to the wireless network connection states. The proposed scheme broadcasts the propagation message in stable connection state, so it can reduce the cache requests and server response time. With the decreasing available network bandwidth by the frequent partial disconnection and disconnection, the proposed scheme dynamically increases the broadcasting ratio of the invalidation messages to minimize the broken message or the loss of message probability. Consequently, the proposed scheme resolves the problems which arise in the invalidation or propagation method in mobile computing environments.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.12
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• pp.685-697
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• 2001

Cache memories are small fast memories used to temporarily hold the contents of main memory that are likely to be referenced by processors so as to reduce instruction and data access time. In this paper, we represent analytical models of instruction fetch process for four types of instruction cache structures that can be used for superscalar processors. In the models, we define various kinds of architectural parameters and take cache miss and branch misprediction into consideration. To prove the correctness of the proposed models, we performed extensive simulations and compared the results with the analytical models. Simulation results showed that the proposed model can estimate the instruction fetch rate accurately within 10% error in most cases. Both analytical model and simulation show that the increase of cache misses reduces the instruction fetch rate more severely than that of branch misprediction does. However, the analytical model can explain the causes of performance degradation which cannot be uncovered by the simulation method only. The model is also able to provide exact relationship between cache miss and branch misprediction for instruction fetch analysis.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.2
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• pp.66-74
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• 2008

Since modem embedded systems need to access, manipulate or store sensitive information, it requires being equipped with cryptographic file systems. However, cryptographic file systems result in poor performance so that they have not been widely adapted to embedded systems. Most cryptographic file systems degrade the performance unnecessarily because of system architecture. This paper proposes ISEA (Indexed and Separated Encryption Approach) that supports for encryption/decryption in system architecture and removes redundant performance loss. ISEA carries out encryption and decryption at different layers according to page cache layer. Encryption is carried out at lower layer than page cache layer while decryption at upper layer. ISEA stores the decrypted data in page cache so that it can be reused in followed I/O request without decryption. ISEA provides page-indexing which divides page cache into cipher blocks and manages it by a block. It decrypts pages partially so that it can eliminate unnecessary decryption. In synthesized experiment of read/write with various cache hit rates, it gives results suggesting that ISEA has improved the performance of encryption file system efficiently.

• The Transactions of the Korea Information Processing Society
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• v.3 no.1
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• pp.118-126
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• 1996

Memory hierarchy is a useful mechanism for improving the memory access speed and making the program space larger by layering the memories and separating program spaces from memory spaces. However, it needs at least two memory accesses for each data reference : a TLB(Translation Lookaside Buffer) access for the address translation and a data cache access for the desired data. If the cache size increases to the multiplication of page size and the cache associativity, it is difficult to access the TLB with the cache in parallel, thereby making longer the critical timing path in the processor. To achieve such parallel accesses, we present the hybrid mapped TLB which combines a direct mapped TLB with a very small fully-associative mapped TLB. The former can reduce the TLB access time. while the latter removes the conflict misses from the former. The trace-driven simulation shows that under given workloads the proposed TLB is effective even when a fully-associative mapped TLB with only four entries is added because the effects of its increased misses are offset by its speed benefits.

• The Transactions of the Korea Information Processing Society
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• v.7 no.8
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• pp.2310-2326
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• 2000

Client-server DBMS based on a data-shipping model can exploit e1ient resources effectively by allowing inter-transaction caching. However, inter-transaction caching raises the need of transactional cache consistency maintenancetTCCM protocol. since each client is able to cache a portion of the database dynamically. Deferred locking(DL) is a new detection-based TCCM scheme designed on the basis of a primary copy locking algorithm. In DL, a number of lock ,ujuests and a data shipping request are combined into a single message packet to minimize the communication overhead required for consistency checking. Lsing a simulation model. the performance of the prolxlsed scheme is compared with those of two representative detection based schemes, the adaptive optimistic concurrency control and the caching two-phase locking. The performance results indicate that DL improves the overall system throughput with a reasonable transaction abort ratio over other detection - based schemes.