• Proceedings of the KSR Conference
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• 2007.05a
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• pp.45-57
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• 2007

During the design phase of a system, which requires high reliability and safety such as aircraft, high speed train and nuclear power plant, reliability engineer must set up the target system reliability. To meet a reliability goal for the system, reliability allocation should be done gradually from the system to its element. For this end, first of all, we need to construct functional block diagram based on the design output and PWBS(Project Work Breakdown System). Another important input data for reliability allocation is the relationship between the cost and the reliability. In this study we investigate various reliability allocation models, which can be applicable to aircraft, vehicle, and power plant, and etc. And we suggest a proper reliability allocation model which can be effectively applicable to KTX-II high speed train to achieve the target system reliability.

• Journal of Satellite, Information and Communications
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• v.6 no.1
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• pp.19-27
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• 2011

In this paper, we propose the data stream allocation algorithms for maximizing sum capacity of downlink multiuser MIMO (Multiple-input Multiple-output) systems with BD (Block Diagonalization). The conventional BD precoding algorithms maximize the capacity by controlling power against channel gain of each user. In multiuser MIMO systems, however, the number of data streams for each user can be used to as another control parameter, which determines the capacity. This paper proposes the data stream allocation algorithm of BD for increasing capacity in multiuser MIMO systems. The proposed algorithm allocates unequal bit stream to each user based on channel matrix of each user for maximizing sum capacity. It is proved that proposed algorithm can achieve the significantly improved sum capacity by computer simulation.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1215-1218
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• 1998

본 논문은 Digital Audio Compression(AC-3) Standard 인 A-52를 기반으로 하였으며 Borland C++3.1 Compiler를 사용하여 AC-3 Decoding Algorithm 구현하였다. Input Stream은 DVD VOB File에서 AC-3 Stream만을 분리하여 사용하며 최종 출력은 16 Bit PCM File이다. AC-3의 Frame구조는 Synchronization Information, Bit Stream Information, Audio Block, Auxiliary Data, Error Check로 구성된다. Aduio Block 은 모두 6개의 Block으로 나뉘어져 있다. BSI와 Side Information을 참조하여 Exponent를 추출하여 Exponent Strategy에 따라 Exponent를 복원한다. 복원된 Exponent 정보를 이용하여 Bit Allocation을 수행하여 각각의 Mantissa에 할당된 Bit수를 계산하고 Stream으로부터 Mantissa를 추출한다. Coupling Parameter를 참조하ㅕ Coupling Channel을 Original Channel로 복원시킨다. Stereo Mode에 대해서는 Rematrixing을 수행한다. Dynamic Range는 Mantissa와 Exponent의 Magnitude를 바꾸는 것으로 선택적으로 사용할 수 있다. Mantissa와 Exponent를 결합하여 Floating Point coefficient로 만든 후 Inverse Transform을 수행하면 PCM Data를 얻을 수 있다. PC에서 듣기 위해서는 Multi Channel을 Stereo나 Mono로 Downmix를 수행한다. 이렇게 만들어진 PCM data는 PCM Data를 재생하는 프로그램으로 재생할 수 있다.

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1082-1091
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• 2000

In Distributed Shared Memory systems, false sharing occurs when two different data items, not shared but accessed by two different processors, are allocated to a single block and is an important factor in degrading system performance. The paper first analyzes shared memory allocation and reference patterns in parallel applications that allocate memory for shared data objects using a dynamic memory allocator. The shared objects are sequentially allocated and generally show different reference patterns. If the objects with the same size are requested successively as many times as the number of processors, each object is referenced by only a particular processor. If the objects with the same size are requested successively much more than the number of processors, two or more successive objects are referenced by only particular processors. On the basis of these analyses, we propose a memory allocation scheme which allocates each object requested by different processors to different pages and evaluate the existing memory allocation techniques for reducing false sharing faults. Our allocation scheme reduces a considerable amount of false sharing faults for some applications with a little additional memory space.

• IE interfaces
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• v.14 no.4
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• pp.394-402
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• 2001

In this study, we deal a spatial scheduling system for the block painting process in the shipbuilding industry. In general, the spatial scheduling for the block painting process is a very complicated task. Because spatial allocation of each block in blasting and painting cells is considered simultaneously. Thus the spatial scheduling for the block painting process is the problem of planning and control of operation, which arises in shipyard. This system is developed for blocks to meet the delivery date given by the shipyard production planning system, to maximize space utilization of blasting and painting cells and to balance workload among working teams. And it has been tested using actual scheduling data from a shipyard and successfully applied in a paint shop in a shipbuilding company.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.5
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• pp.74-82
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• 2011

SSD has a limitation of number of erase/write cycles and does not allow in-place update unlike the hard disk because SSD is composed of an array of NAND flash memory. Thus, FTL is used to effectively manage SSD of having different characteristics from traditional disk. FTL has page, block, log-block mapping method. Among then, when log-block mapping method such as BAST and FAST is used, the performance of SSD is degraded because frequent merge operations cause lots of pages to be copied and deleted. This paper proposes a data allocation and replacement method based on access frequency by allocating PRAM as checking area of access frequency, log blocks, storing region of hot data in SSD. The proposed method can enhance the performance and lifetime of SSD by storing cold data to flash memory and storing log blocks and frequently accessed data to PRAM and then reducing merge and erase operations. Besides, a data replacement method is used to increase utilization of PRAM which has limitation of capacity. The experimental results show that the ratio of erase operations of the proposed method is 46%, 38% smaller than those of BAST and FAST and the write performance of the proposed method is 34%, 19% higher than those of BAST and FAST, and the read performance of the proposed method is 5%, 3% higher than those of BAST and FAST, respectively.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.18 no.2
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• pp.511-527
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• 2024

This paper proposes a block-based self-organizing time-division multiple access (BSO-TDMA) protocol for very high frequency (VHF) data exchange system (VDES) in shipborne ad-hoc networks (SANETs). The BSO-TDMA reduces the collisions caused by the simultaneous transmission of automatic identification system (AIS) messages by uniformly allocating channel resources using a block-wise frame. For this purpose, the BSO-TDMA includes two functional operations: (1) frame configuration and (2) slot allocation. The first operation consists of block division and block selection. A frame is divided into multiple blocks, each consisting of fixed-size subblocks, by using the reporting interval (RI) of the ship. Then, the ship selects one of the subblocks within a block by considering the number of occupied slots for each subblock. The second operation allocates the slots within the selected subblock for transmitting AIS messages. First, one of the unoccupied slots within the selected subblock is allocated for the periodic transmission of position reports. Next, to transmit various types of AIS messages, an unoccupied slot is randomly selected from candidate slots located around the previously allocated slot. Experimental simulations are conducted to evaluate the performance of BSO-TDMA. The results show that BSO-TDMA has better performance than that of the existing SOTDMA.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.253-256
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• 2001

This paper describes a high speed MAC(Media Access Control) function chip for IEEE 802.11 MAC layer protocol. The MAC chip has control registers and interrupt scheme for interface with CPU and deals with transmission/reception of data as a unit of frame. The developed MAC chip is composed of protocol control block, transmission block, and reception block which supports the BCF function in IEEE 802.11 specification. The test suite which is adopted in order to verify operation of the MAC chip includes various functions, such as RTS-CTS frame exchange procedure, correct IFS(Inter Frame Space)timing, access procedure, random backoff procedure, retransmission procedure, fragmented frame transmission/reception procedure, duplicate reception frame detection, NAV(Network Allocation Vector), reception error processing, broadcast frame transmission/reception procedure, beacon frame transmission/reception procedure, and transmission/reception FIEO operation. By using this technique, it is possible to reduce the load of CPU and firmware size in high speed wireless LAN system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.574-577
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• 2007

While disk can be overwritten on updating data, because flash memory can not be overwritten on updating data, new data are updated in new area. If data are frequently updated, garbage collection, which is achieved by erasing blocks, should be performed to reclaim new area. Hence, because the number of erase operations is limited due to characteristics of flash memory, every block should be evenly written and erased. However, if data with access locality are processed by cost benefit algorithm with separation of hot block and cold block, though the performance of processing is high, wear-leveling is not even. In this paper, we propose CB-MB (Cost Benefit between Multi Bank) algorithm in which hot data are allocated in one bank and cold data in another bank, and in which role of hot bank and cold bank is exchanged every period. CB-MB showed that its performance was similar to that of others for uniform workload, however, the method provides much better performance than that of others for workload of access locality.

• Journal of Communications and Networks
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• v.13 no.3
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• pp.250-256
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• 2011

A two-way relaying (TWR) system is analyzed, where two source terminals with unequal numbers of antennas exchange data via an amplify-and-forward relay terminal with a single antenna. In the system considered herein, the link quality between the sources and relay can generally be asymmetric due to the nonidentical antenna configuration, power allocation, and relay location. In such a general setup, accurate bounds on the average sum rate (ASR) are derived when beamforming or orthogonal space time block coding is employed at the sources. We show that the proposed bounds are almost indistinguishable from the exact ASR under various system configurations. It is also observed that the ASR performance of the TWR system with unequal numbers of source antennas is more sensitive to the relay location than to the power allocation.