• Journal of Korean Institute of Industrial Engineers
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• v.14 no.1
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• pp.1-15
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• 1988

DS1 transmission systems use framing bit errors, bipolar violations and code-detected errors to estimate the bit error rate when determining errored and severely errored seconds. Using the coefficient of variation under the memoryless binary symmetric channel assumption, a basic framework to evaluate these estimation schemes is proposed to provide a practical guideline in determining errored and severely errored seconds which are fundamental in monitoring the real-ime error performance of DS1 transmission systems carrying live traffic. To evaluate the performance of the cyclic redundancy check code (CRC), a computer simulation model is used. Several drawbacks of the superframe format in association with real time error performance monitoring are discussed. A few recommendations are suggested in measuring errored and severely errored seconds, and determining service limit alarms through the use of the superframe format. Furthermore, we propose a new robust scheme for determining service limit alarms which take into consideration the limitations of some estimation schemes for the time interval of one second.

• Journal of IKEEE
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• v.22 no.4
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• pp.896-900
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• 2018

Traditionally, Linear Shift Feedback Register (LFSR) has been widely employed to implement Cyclic Redundant Check (CRC) codes for a serial input. Since many applications including network and storage systems demand as high throughput as ever, various efforts have been made to implement CRC hardware to support parallel inputs. Among various parallel schemes, the look-ahead scheme is one of the most widely used schemes due to its short critical path. However, it is very cumbersome to design HDL codes for parallel CRC codes since the look-ahead scheme is inevitable to consider how register and input values move in the next cycles. Thus, this paper proposes a novel CRC hardware generator, which automatically produces HDL codes given a CRC polynomial and parallel factor. The experimental results verify the applicability to use the proposed generator by analyzing the synthesis results from the generated HDL code.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.835-842
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• 2009

DVB-SSP is a new broadcasting system for hybrid satellite communications, which supports mobile handheld systems and fixed terrestrial systems. However, a critical factor must be considered in upper layer decoding which including erasure Reed-Solomon error correction combined with cyclic redundancy check. If there is only one bit error in an IP packet, the entire IP packet is considered as unreliable bytes, even if it contains correct bytes. IF, for example, there is one real byte error, in an If packet of 512 bytes, 511 correct bytes are erased from the frame. Therefore, this paper proposed two kinds of upper layer decoding methods; LLR-based decoding and hybrid decoding. By means of simulation we show that the performance of the proposed decoding algorithm is superior to that of the conventional one.

• Journal of Korea Society of Digital Industry and Information Management
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• v.11 no.3
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• pp.31-43
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• 2015

In this paper, we discuss a code generation technique for custom transport triggered architecture (TTA) from a high-level language structure. This methodology is implemented by using TTA-based Co-design Environment (TCE) tool. The results show how the scheduler exploits instruction level parallelism in the custom target architecture and source program. Thus, the scheduler generates parallel TTA instructions using lower cycle counts than the sequential scheduling algorithm. Moreover, we take Tensilica tool to make a comparison with TCE. Because of the efficiency of TTA, TCE takes less execution cycles compared to Tensilica configurations. Finally, this paper shows that it requires only 7 cycles to generate the parallel TTA instruction set for implementing Cyclic Redundancy Check (CRC) applications as an input design, and presents the code generation technique to move complexity from the processor software to hardware architecture. This method can be applicable lots of channel Codecs like CRC and source Codecs like High Efficiency Video Coding (HEVC).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9C
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• pp.843-850
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• 2003

Turbo coding and turbo processing have been known as methods close to Shannon limit in the aspect of wireless MIMO communications similarly to wireless single antenna communication. The iterative processing can maximize the mutual effect of coding and interference cancellation, but turbo coding has not been used for turbo processing because of the inherent decoding process delay. This paper proposes a turbo coded MIMO system with adaptive turbo parallel space-time (Turbo-PAST) processing for high-speed wireless communications and a enhanced cyclic redundancy check (E-CRC) scheme as an efficient and simple priori stopping criterion. Simulation results show that the Turbo-PAST outperforms conventional system with 1.3dB and the proposed E-CRC scheme effectively reduces the amount of turbo processing iterations from the point of average number of iterations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2227-2234
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• 2009

DVB-SSP is a new broadcasting system for hybrid satellite communications, which supports mobile handheld systems and fixed terrestrial systems. An upper layer, including erasure Reed-Solomon error correction combined with cyclic redundancy check. However, a critical factor must be considered in upper layer decoding. If there is only one bit error in an IP packet, the entire IP packet is considered as unreliable bytes, even if it contains correct bytes. If, for example, there is one real byte error, in an IP packet of 512 bytes, 511 correct bytes are erased from the frame. Therefore, this paper proposed upper layer decoding methods; LLR-based decoding. By means of simulation we show that the performance of the proposed decoding algorithm is superior to that of the conventional one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11C
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• pp.889-895
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• 2010

MIMO system generally requires more than one antenna at the communication device. However, many wireless devices are limited by size, cost or hardware complexity to one antenna. To overcome such restrictions, we used a new technique, called cooperative communication. We propose a new cooperative transmission strategy system using cross-layer coding method base on H-ARQ for optimal communication. Proposed cooperative H-ARQ system that can improve the above problems and can get the better performance. In proposed cooperative system with H-ARQ method, if the received signal from source node is satisfied by the destination preferentially, the destination transmit ACK message to both relay node and source node, and then recovers the received signal. In addition, if ARQ message indicates NACK message, relay node operates selective retransmission. Based on the simulation results in aspect to BER performance and throughput, the proposed method which combined cooperative system with H-ARQ based on cross-layer coding can improve spectral efficiency reliability of system compared with that of general one by one system.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.2
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• pp.658-675
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• 2022

This paper presents a fast-simplified successive cancellation (SC) flipping (Fast-SSC-Flip) decoding algorithm for polar code. Firstly, by researching the probability distribution of the number of error bits in a node caused by channel noise in simplified-SC (SSC) decoder, a measurement criterion of node reliability is proposed. Under the guidance of the criterion, the most unreliable nodes are firstly located, then the unreliable bits are selected for flipping, so as to realize Fast-SSC-Flip decoding algorithm based on node reliability (NR-Fast-SSC-Flip). Secondly, we extended the proposed NR-Fast-SSC-Flip to multiple node (NR-Fast-SSC-Flip-ω) by considering dynamic update to measure node reliability, where ω is the order of flip-nodes set. The extended algorithm can correct the error bits in multiple nodes, and get good performance at medium and high signal-to-noise (SNR) region. Simulation results show that the proposed NR-Fast-SSC-Flip decoder can obtain 0.27dB and 0.17dB gains, respectively, compared with the traditional Fast-SSC-Flip [14] and the newly proposed two-bit-flipping Fast-SSC (Fast-SSC-2Flip-E2) [18] under the same conditions. Compared with the newly proposed partitioned Fast-SSC-Flip (PA-Fast-SSC-Flip) (s=4) [18], the proposed NR-Fast-SSC-Flip-ω (ω=2) decoder can obtain about 0.21dB gain, and the FER performance exceeds the cyclic-redundancy-check (CRC) aided SC-list (CRC-SCL) decoder (L=4).