• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.17 no.1
• /
• pp.116-123
• /
• 2003

In this paper, interleaved boost converter is applied as a pre-regulator in switched mode power supply. The pre-regulator plays a role to improve power factor. Interleaved Boost Power Factor Corrector(IBPFC) can reduce input current ripple as a single voltage control loop only without inner current loop, because input current is divided each 50% by two switching devices. Each converter cell is also operated in discontinuous current mode and inductor current of each converter is discontinuous. Total input current which is composed by each converter cell is continuous current. Thus, IBPFC is able to improve input current ripple. IBPFC operating in discontinuous current mode can be classified as six modes from switching state and be carried out state space averaging small signal modeling. A control transfer function is obtained according to the modeling. Single voltage control loop is also constructed by the control transfer function. From experimental result, improvement of power factor and input current ripple are verified.

• ETRI Journal
• /
• v.39 no.4
• /
• pp.582-591
• /
• 2017

To address the wire complexity problem in large-scale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current-mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using $0.25-{\mu}m$ CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10-mm wire. They also reduce the power-delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.

• Journal of Ocean Engineering and Technology
• /
• v.27 no.4
• /
• pp.83-89
• /
• 2013

A numerical scheme based on a mode superposition method is presented for the dynamic response analysis of a top-tensioned riser (TTR) under sheared current loads. The natural frequencies and mode shapes of the TTR have been calculated analytically for a beam with a slowly varying tension and pinned-pinned boundary conditions at the top and bottom ends. The lift coefficients and corresponding amplitudes used to estimate the vortex-induced modal force and damping for each mode were predicted via iterative calculations based on the input and output power balancing concept. Here, the power-in regions were controlled by the normal distribution function, for which the center was coincident with the lock -in location by local vortex-shedding, and the range was defined by the constant standard deviation for the reduced velocity by the local current speed. Finally, dynamic responses such as root-mean-squared displacement and stress were calculated using the mode superposition technique. In order to verify the presented scheme, a numerical calculation was performed for a TTR under an arbitrary linearly sheared current and linearly varying tension. A comparison with the results of the existing software showed that the presented scheme could give reliable and feasible solutions. Case studies were performed to investigate the effects of various current loads and tensions.

• Journal of the Microelectronics and Packaging Society
• /
• v.13 no.4
• /
• pp.57-63
• /
• 2006

For chip-stack package applications, Cu filling characteristics into trench vias of $75{\sim}10\;{\mu}m$ width and 3 mm length were investigated with variations of electroplating current density and current mode. At $1.25mA/cm^{2}$ of DC mode, Cu filling ratio higher than 95% was obtained for trench vias of $75{\sim}35{\mu}m$ width. When electroplated at DC $2.5mA/cm^{2}$, Cu filling ratios became inferior to those processed at DC $1.25mA/cm^{2}$. Pulse current mode exhibited Cu filling characteristics superior to DC current mode.

• Journal of Power Electronics
• /
• v.19 no.1
• /
• pp.254-264
• /
• 2019

This paper proposes an indirect current control technique based on a proportional resonant (PR) approach for the seamless mode transfer of utility interactive inverters. Direct-current and voltage hybrid control methods have been used for inverter control under grid-connected and islanded modes. A large bandwidth can be selected due to the structure of single-loop control. However, this results in poor dynamic transients due to sudden changes of the controller during mode changes. Therefore, inverter control based on indirect current is proposed to improve the dynamic transients by consistently controlling the output voltage under all of the operation modes. A PR-based indirect current control topology is used in this study to maintain the load voltage quality under all of the modes. The design processes of the PR-based triple loop are analyzed in detail while considering the system stability and dynamic transients. The mode transfer techniques are described in detail for both sudden unintentional islanding and islanded mode voltage quality improvements. In addition, they are described using the proposed indirect control structure. The proposed method is verified by the PSiM simulations and laboratory-scale VDER-HILS experiments.

• Proceedings of the IEEK Conference
• /
• 2002.07b
• /
• pp.755-758
• /
• 2002

This paper presents a second-generation CMOS current conveyor (CCII) consisting of a rail-to-rail complementary N- and P-channel differential input stage for the voltage input, a class AB push-pull stage for the current input, and current mirrors far the current outputs. The CCII was implemented using a double-poly triple-metal 0.6 ${\mu}$m n-well CMOS process, to confirm its operation experimentally. A prototype chip achieves a rail-to-rail swing ${\pm}$2.4 V under ${\pm}$2.5 V power supplies and shows the exact voltage and current following performances up to 100 MHz. Because of its high performances, the CCII proposed herein is quite useful for a building block of current-mode circuits. The applications of the proposed CCII to current-mode filters are also described.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.6 no.5
• /
• pp.423-431
• /
• 2001

This paper proposes a new active common-mode voltage damper circuit that is capable of suppressing a common-mode voltage produced in the PWM VSI-fed induction motor drives. The new active common mode voltage damper is consists of a four-level half-bridge Inverter and a common mode transformer with a blocking capacitor. In order to reduce the common mode voltage and high frequency leakage current the active common mode damper applies to the PWM inverter system the compensated voltage of which the amplitude is the same as the common mode voltage and of which the polarity is opposite to the common mode voltage. Simulated using P-SPICE and experimental results show that common-mode voltage damper makes contributions to reducing a high frequency leakage current and common-mode voltage.

• The Transactions of the Korean Institute of Electrical Engineers B
• /
• v.52 no.5
• /
• pp.230-237
• /
• 2003

Current mode control has been used for DC to DC converters for over twenty years. There are many different control schemes which use the inductor current signal in one way or another to control the DC to DC converter. In this paper, the state space averaging technique is applied for the analysis of flyback type current mode control circuit. We made real converter for the guarantee of stable output characteristic and proper design of feedback circuit. The validity of proposed method is verified from test result. The improvement of stability is confirmed by sinusoidal signal injection method with isolated transformer. It is known that phase margin is sufficient and gain crossover frequency fc is early 1/5 of switching frequency, fs, from the experimental result with frequency response analyzer.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.1077-1080
• /
• 1998

In this paper, a simple low-power current-mode CMOS wotage reference circuit is proposed. The reference circuit of enhancement-mode MOS transistors and resistors. Temperature compensation is made by adding a current component proportional to a thermal voltage to a current component proportional to a threshold voltage. The designed circuit has been simulated using a $0.65\mu\textrm{m}$ n-well CMOS process parameters. The simulation results show that the reference circuit has a temperature coefficient less than $7.8ppm/^{\circ}C$ and a power-supply(VDD) coefficient less than 0.079%/V for a temperature range from $-30^{\circ}C$ to $130^{\circ}C$ and a VDD range from 4.0V to 12V. The power consumption is 105㎼ for VDD=5V and $T=30^{\circ}C.$ The proposed reference circuit can be designed to generate a wide range of reference voltages owing to its current-mode operation.

• Journal of Electrical Engineering and Technology
• /
• v.13 no.6
• /
• pp.2310-2318
• /
• 2018

Critical conduction mode (CRM) operation is more efficient than continuous conduction mode (CCM) operation at low power levels because of the valley switching of switches and elimination of the reverse recovery losses of boost diodes. When using a sensorless digital control method, an error occurs between the actual and the estimated current. Because of the error, it operates as CCM or discontinuous conduction mode (DCM) during CRM operation and also has an adverse effect on THD of input current. In this paper, a current sensorless technique is presented in an inverter system using a bridgeless boosted power factor correction converter, and a compensation method is proposed to reduce CRM calculation error. The validity of the proposed method is verified by simulation and experiment.