• ETRI Journal
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• 제28권4호
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• pp.486-494
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• 2006

Two current-mode and/or voltage-mode quadrature oscillator circuits each using one fully-differential second-generation current conveyor (FDCCII), two grounded capacitors, and two (or three) grounded resistors are presented. In the proposed circuits, the current-mode quadrature signals have the advantage of high-output impedance. The oscillation conditions and oscillation frequencies are orthogonally (or independently) controllable. The current-mode and voltage-mode quadrature signals can be simultaneously obtained from the second proposed circuit. The use of only grounded capacitors and resistors makes the proposed circuits ideal for integrated circuit implementation. Simulation results are also included.

• 전자공학회논문지C
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• 제34C권11호
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• pp.56-65
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• 1997

In this paper, a design of current-mode continuous-time filters for low voltage and high frequency applictions using complementary bipolar current mirror paris is presented. The proposed current-mode filters consist of simple bipolar current mirrors and capacitors and are quite suitable for monolithic integrtion. Since the design method of the proposed curent-mode filters is based on the integrator type of realization, it can be used for a wide range of applications. And the cutoff frequency of th efilters can be easily changed by the DC cntrolling current. As design examples, the 5th order butterworth filters are designed by cascade and leapfrog methods with tunable cutoff frequencies from 30MHz to 100MHz. The characteristics of the designed current mode filters are simulated and examined by SPICE using standard bipolar transistor parameters.

• Journal of Power Electronics
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• 제11권1호
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• pp.59-63
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• 2011

This paper presents the modeling of the sampling effect in the p-type average current mode control. The prediction of the high frequency components near half of the switching frequency in the current loop gain is given for the p-type average current mode control. By the proposed model, the prediction accuracy is improved when compared to that of conventional models. The proposed method is applied to a buck converter, and then the measurement results are analyzed.

• 대한전자공학회논문지SD
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• 제45권8호
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• pp.37-43
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• 2008

본 논문에서는 고속 동작에서 동적 전력 소비와 정적 전력 소비를 동시에 줄일 수 있는 self-timed current-mode Logic(STCML)을 제안한다. 제안된 로직 스타일은 펄스 신호로 가상 접지를 방전하여 로직 게이트의 누설 전류(subthreshold leakage current)를 획기적으로 감소시켰다. 또한, 본 로직은 개선된 self-timing buffer를 사용하여 동적모드 동작 시 발생되는 단락 회로 전류(short-circuit current)를 최소화하였다. 80-nm CMOS 공정을 이용하여 실시한 비교 실험 결과, 제안된 로직 스타일은 기존의 대표적인 current-mode logic인 DyCML에 비하여 동일한 시간 지연에서 26 배의 누설 전력 소비를 줄이고 27%의 동적 전력 소비를 줄일 수 있었다. 또한, 대표적인 디지털 로직 스타일인 DCVS와의 비교 결과, 59%의 누설 전력 소비감소 효과가 있었다.

• Journal of Electrical Engineering and Technology
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• 제10권5호
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• pp.1989-2000
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• 2015

In this paper, digital peak current mode control for single phase H-bridge inverters is developed and implemented. The digital peak current mode control is achieved by directly controlling the PWM signals by cycle-by-cycle current limitation. Unlike the DC-DC converter where the output voltage always remains in the positive region, the output of DC-AC inverter flips from positive to negative region continuously. Therefore, when the inverter operates in negative region, the control should be changed to valley current mode control. Thus, a novel control logic circuit is required for the function and need to be analyzed for the hardware to track the sinusoidal reference in both regions. The problem of sub-harmonic instability which is inherent with peak current mode control is also addressed, and then proposes the digital slope compensation in constant-sloped external ramp to suppress the oscillation. For unipolar PWM switching method, an adaptive slope compensation in digital manner is also proposed. In this paper, the operating principles and design guidelines of the proposed scheme are presented, along with the performance analysis and numerical simulation. Also, a 200W inverter hardware prototype has been implemented for experimental verification of the proposed controller scheme.

• 전력전자학회논문지
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• 제10권3호
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• pp.219-225
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• 2005

본 논문에서는 평균전류모드제어를 이용하는 컨버터의 전류응답을 예측할 수 있는 새로운 이산시간 소신호 모델을 구한다. 평균전류모드제어는 최대전류모드제어와 달리 전류제어를 위해 복잡한 보상기 회로를 사용하므로 컨버터의 동작 특성 해석이 어렵다. 평균전류모드제어를 사용하는 컨버터의 소신호 전류응답을 예측하기 위해 샘플러모델을 제안하고, 이 모델로부터 새로운 이산시간 소신호 모델을 구한다. 제안된 방식은 기존 방식과 달리 복잡한 형태의 보상기를 사용하는 컨버터에도 적용 가능하다. 제안한 새로운 이산시간 소신호 모델을 이용한 예측 결과를 스위칭 모델 시뮬레이션 프로그램인 PSIM을 이용한 시뮬레이션 결과 및 실험결과와 비교하여 제안한 새로운 이산시간 소신호 모델의 우수성을 보인다.

• 한국초전도ㆍ저온공학회논문지
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• 제14권3호
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• pp.23-27
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• 2012

This paper aims to evaluate the feasibility of using no-insulation High Temperature Superconducting (HTS) coil in persistent current mode system. A HTS coil in persistent current mode system usually includes one or more non-superconducting joints in its circuit. And the current decaying rate of the coil is affected by the resistance of joint in persistent current circuit. If the resistance of joint is large, decaying rate of the current drastically increases. Therefore, reducing the joint resistance of the HTS coil is very important in persistent current mode system. In this paper, the no-insulation HTS coil is suggested as a way to reduce the joint resistance with the embedded parallel contact resistance naturally made by no-insulation winding method. Two small coils are fabricated with insulation and no-insulation winding method, and persistent current mode system experiment of each coil is preformed and analyzed.

• 한국전자통신학회논문지
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• 제8권10호
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• pp.1477-1483
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• 2013

연속시간 전류모드 기저대역 채널선택 필터 설계를 위하여 전류이득과 단위이득 주파수를 개선시킨 저전압 선형 캐스코드 전류모드 적분기를 제안하였다. 제안된 전류모드 적분기는 CMOS 상보형 회로로 구성된 완전 차동 형태의 입 출력단으로 구성하였으며, 여기에 캐스코드 트랜지스터를 추가시킴으로써 바이어스 단을 구성하여 선형영역에서 동작시켜 저전압 구조에 적합하도록 설계하였다. 이 때 바이어스 전압을 선택적으로 제어하여 주파수 대역이 가변될 수 있도록 설계하였다. 시뮬레이션 결과를 통해 설계한 선형 캐스코드 전류모드 적분기가 저전압 동작, 전류 이득 및 단위이득 주파수 등 모두 만족할 만한 특성을 가지고 있음을 확인하였다.

• 한국초전도ㆍ저온공학회논문지
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• 제12권1호
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• pp.56-60
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• 2010

Recently, many researches have been carried out for a high temperature superconducting (HTS) magnet which is advantageous in high critical current density and critical temperature. In HTS magnet, however, critical current is decreased by perpendicular magnetic field and persistent current is hard to maintain due to a low index value and high joint resistance compared with low temperature superconducting (LTS) magnet. In this paper, the HTS magnet using BSCCO wire was simulated through finite element method (FEM) and manufactured. we experimentally investigated operating characteristics of the compensating mode of the HTS magnet for current decay and made a comparison between persistent current mode and compensating mode. A feedback control unit was used to sustain current within specified ranges with defined upper and lower limits.

• 전력전자학회논문지
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• 제24권2호
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• pp.134-137
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• 2019

A wide-bandwidth current controller is required for fast charging/discharging of super capacitor applications. Peak current mode is generally used to accomplish fast charging/discharging because this mode has fast response characteristics. However, the peak current mode control must have a slope compensation function to restrain sub-harmonics oscillation. The slope must be changed accordingly if the controlled output voltage is varied. However, changing the slope for every changed output voltage is not easy. The other solution, selecting the slope as the maximum value, causes a slow response problem to occur. Therefore, we propose a hybrid mode controller that uses a peak current and a newly specified valley current. Through the proposed hybrid mode control, the sub-harmonic oscillation does not occur when the duty is larger than 0.5 because of the fast response.